VL22 同步FIFO

最新推荐文章于 2024-10-31 21:31:19 发布

计科小学生233

最新推荐文章于 2024-10-31 21:31:19 发布

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分类专栏： verilog 文章标签： fpga开发

本文链接：https://blog.csdn.net/ChenGz233/article/details/125174750

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如图FIFO和RAM的关系

在这里插入图片描述

rtl代码：

`timescale 1ns/1ns
/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output reg				wfull	,
	output reg				rempty	,
	output wire [WIDTH-1:0]	rdata
);
    
    reg [$clog2(DEPTH)-1:0] waddr, raddr;
    reg [$clog2(DEPTH)  :0] cnt;
    
       always@(posedge clk or negedge rst_n) begin
           if(~rst_n) begin
                waddr <= 0;
                raddr <= 0;
           end
            else begin 
                if(winc & ~wfull) 
                    waddr <= waddr+1;
                else 
                    waddr <=  waddr;

                if(rinc & ~rempty) 
                   raddr <= raddr+1;
                else 
                    raddr <=  raddr;
            end
       end
    

     
   always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            cnt <= 0;
        /*else if(winc&~wfull)*/
        else begin
            if(winc&~wfull & cnt < DEPTH-1 & rinc&~rempty & cnt > 0 )
                cnt <= cnt;
            else if(winc&~wfull & cnt < DEPTH-1)
                cnt <= cnt + 1;
            else if(rinc&~rempty & cnt > 0)
                cnt <= cnt - 1;
             else
             cnt <= cnt;
         end
    end
     
        always@(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            wfull  <= 1'd0;
            rempty <= 1'd1;
        end
        else begin
        /* if(cnt == DEPTH-1)*/
            if(cnt == DEPTH-1)
                wfull  <=1'd1;
            else
               wfull  <= 1'd0;
            
            if(cnt == 0)
                rempty <= 1'd1;
            else
                rempty <= 1'd0;
        end
    end
     
    dual_port_RAM #(
        .DEPTH(DEPTH       ),
        .WIDTH(WIDTH       )
    )
    myRAM(
        .wclk (clk         ),
        .wenc (winc&~wfull ),
        .waddr(waddr       ),
        .wdata(wdata       ),
        .rclk (clk         ),
        .renc (rinc&~rempty),
        .raddr(raddr       ),
        .rdata(rdata       )
    );
    
endmodule

testbench 代码

`timescale 1ns / 1ps
module dual_port_RAM_tb();

parameter	WIDTH = 8;
parameter 	DEPTH = 16;

reg				clk;
reg 			rst_n;
reg 			winc;
reg 			rinc;
reg 		    [WIDTH-1:0]	wdata;

wire				wfull;
wire				rempty;
wire                [WIDTH-1:0]	rdata;
	
	
	 sfifo   #(
	.WIDTH  (WIDTH),
	.DEPTH(DEPTH)
)sfifo_1(
	.clk	(clk)	, 
	.rst_n(rst_n)	,
	.winc(winc)	,
	.rinc(rinc)	,
	.wdata(wdata)	,

	.wfull(wfull)	,
	.rempty(rempty)	,
	.rdata(rdata)
);
   real         CYCLE_200MHz = 5 ; //
    always begin
        clk = 0 ; #(CYCLE_200MHz/2) ;
        clk = 1 ; #(CYCLE_200MHz/2) ;
    end
     initial begin
     
     rst_n = 0; rinc = 0; winc = 0; wdata = 8'd0;
     #5 rst_n = 1; rinc = 0; winc = 0; wdata = 8'd1;
     
     #5 rst_n = 1; rinc = 1; winc = 0;wdata = 8'd1;
     
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd2;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd6;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd3;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd4;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd5;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd6;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd8;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd9; 
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd3;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd4;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd5;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd6;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd7;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd8;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd9;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd3;
     #5 rst_n = 1; rinc = 0; winc = 1; wdata = 8'd4;
                    
     #5 rst_n = 1; rinc = 0; winc = 0; wdata = 8'd4;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 1;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 1;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     #5 rst_n = 1; rinc = 1; winc = 0;
     
     
     
     
     
     
     
      $stop;
 end
    
endmodule