1.Timer System Control Register 1(TSCR1)
寄存器编号 | 描述 |
7 | Timer Enable |
0 Disables the main timer, including the counter. Can be used for reducing power consumption. | |
1 Allows the timer to function normally. |
2.Timer Interrupt Enable Register(TIE)
寄存器编号 | 描述 |
0~7 | Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in |
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, | |
the corresponding flag is enabled to cause a interrupt. |