数字IC设计工程师笔试面试经典100题

数字IC设计工程师笔试面试经典100题

https://blog.csdn.net/qq_41394155/article/details/89349935

ASIC–模拟版图工程师

https://blog.csdn.net/qq_41394155/article/details/89208062

ASIC–DFT可测性设计工程师

https://blog.csdn.net/qq_41394155/article/details/88365028

.vimrc

https://blog.csdn.net/qq_41394155/article/details/84666832

systemVerilog知识汇总

https://blog.csdn.net/qq_41394155/article/details/83313379

IC验证_综合知识

https://blog.csdn.net/qq_41394155/article/details/83142955

IC验证中Makefile文件

https://blog.csdn.net/qq_41394155/article/details/83108213

#!/bin/sh
RTL_PATH=-f ../../rtl/rtl.fl
TB_PATH=../../verif
VERB=UVM_DEBUG
SEED=$(shell date +%s)
TEST=
N=0
OUT_DIR=./logs
TEST_ID +=${TEST}_${N}
VPD=+vpdfile+${TEST_LOG}/${TEST_ID}.vpd
TEST_LOG+${OUTPUT_DIR}/${TEST_ID}
COV =-cm line+cond+fsm+tgl -cm_dir ./logs/COV
COV += -cm_hier exclude_bist.fl
all:clean comp run
 
regr:
    make comp
    make run TEST=sramc_test_addr_100 N=0
    make run TEST=sramc_test_rand_hsize HSIE_W=0 HSIZE+R=0 N=1
comp:
    vcs -mcfu -sverilog -ntb_opts uvm -debug -timescale=1ns/1ns \
    $(RTL_PATH) \
    +incdir+../tb \
    +incdir+../agent/ahb \
    +incdir+../tests \
    +incdir+../test/seqlib \
    +incdir+../env \
    ../agent/ahb/ahb_pkg.sv \
    ../agent/ahb/ahb_if.sv \
    ../env/sramc_env_pkg.sv \
    ../test/sramc_test_pkg.sv \
    ../tb/sramc_tb.sv \
    $(COV) -l comp.log
 
run:
    rm -rf logs/${TEST_ID}
    mkdir logs/${TEST_ID}
    ./simv +VPD+ON \
    +UVM_TESTNAME=${TEST} +UVM_VERBOSITY=${VERB} +ntb_random_seed=${SEED} -l ${TEST_LOG}/${TEST_ID}.log \
    $(VPD) $(COV) -cm_name $(TEST_ID)
 
ral:xls2csv csv2sv
 
xls2csv:
    ./scripts/pthon xlsx2csv.py -s1 ../../doc/register_map.xlsx > ./reg_map.csv
 
csv2sv:
    ./scripts/perl uvm_ral_gen.pl reg_map_tbl ./reg_map.csv -module_name apb
    mv ./apb_*.sv ../env/reg_model/
 
dve:
    dve -vpd vcdplus.vpd&
urg:
    urg -dir simv.vdb -report both
clean:
    rm -rf csrc somv* *.log DVEfiles ucli.key logs 

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