Shift registers

verilog 数字模块练习

2017.03.17

// One-bit wide, N-bit long shift register

module basic_shift_register 
#(parameter N=256)
(
    input clk, enable,
    input sr_in,
    output sr_out
);

    // Declare the shift register
    reg [N-1:0] sr;

    // Shift everything over, load the incoming bit
    always @ (posedge clk)
    begin
        if (enable == 1'b1)
        begin
            sr[N-1:1] <= sr[N-2:0];
            sr[0] <= sr_in;
        end
    end

    // Catch the outgoing bit
    assign sr_out = sr[N-1];

endmodule

---

// One-bit wide, N-bit long shift register with asynchronous reset

module basic_shift_register_asynchronous_reset
#(parameter N=256)
(
    input clk, enable, reset,
    input sr_in,
    output sr_out
);

    reg [N-1:0] sr;

    always @ (posedge clk or posedge reset)
    begin
        if (reset == 1'b1)
        begin
            // Load N zeros 
            sr <= {N{1'b0}};
        end
        else if (enable == 1'b1)
        begin
            sr[N-1:1] <= sr[N-2:0];
            sr[0] <= sr_in;
        end
    end

    assign sr_out = sr[N-1];

endmodule

---

// Barrel shifter

module barrel_shifter
#(parameter M=8, parameter N=2**M)
(
    input [N-1:0] data,
    input [M-1:0] distance,
    input clk, enable, shift_left,
    output reg [N-1:0] sr_out
);

    // Declare temporary registers
    reg [2*N-1:0] tmp;

    // Shift/rotate in the specified direction and
    // by the specified amount
    always @ (posedge clk)
    begin
        tmp = {data,data};

        if (enable == 1'b1)
            if (shift_left)
            begin
                tmp = tmp << distance;  
                sr_out <= tmp[2*N-1:N];
            end
            else
            begin
                tmp = tmp >> distance;
                sr_out <= tmp[N-1:0];
            end
    end

endmodule

---

// Basic 64-stage shift register with multiple taps

module basic_shift_register_with_multiple_taps
#(parameter WIDTH=8, parameter LENGTH=64)
(
    input clk, enable,
    input [WIDTH-1:0] sr_in,
    output [WIDTH-1:0] sr_tap_one, sr_tap_two, sr_tap_three, sr_out
);

    // Declare the shift register
    reg [WIDTH-1:0] sr [LENGTH-1:0];

    // Declare an iterator
    integer n;

    always @ (posedge clk)
    begin
        if (enable == 1'b1)
        begin
            // Shift everything over, load the incoming data
            for (n = LENGTH-1; n>0; n = n-1)
            begin
                sr[n] <= sr[n-1];
            end

            // Shift one position in
            sr[0] <= sr_in;
        end
    end

    assign sr_tap_one = sr[LENGTH/4-1];
    assign sr_tap_two = sr[LENGTH/2-1];
    assign sr_tap_three = sr[3*LENGTH/4-1];

    // Catch the outgoing data
    assign sr_out = sr[LENGTH-1];

endmodule