HDLbits Q3A,B,C

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    parameter A=2'd0,S0=2'd1,S1=2'd2,S2=2'd3;
    reg [1:0] state, next;
    reg [1:0] cnt;
    reg en;
    always @(*) begin
        case(state)
            A: 	next<= s ? S0:A;
            S0:	next<= S1;
            S1:	next<= S2;
            S2: next<= S0;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset) 
            state<=A;
        else
            state<=next;
    end
    
    always @(posedge clk) begin
        case(state)
            A: 	{en,cnt}<= 3'b0;
            S0:	cnt<= w;
            S1:	{en,cnt}<= {1'b0,w ? (cnt+1'b1):cnt};
            S2: {en,cnt}<= {((cnt==2'b10 && w==0) || (cnt==2'b01 && w==1)),w ? (cnt+1'b1):cnt};
 			default: cnt<=0;
        endcase
    end
    
    
    
    assign z = en==1'b1 && state==S0;

endmodule

Q3B_answer

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    
    parameter S1=3'd0,S2=3'd1,S3=3'd2,S4=3'd3,S5=3'd4;
    reg [2:0] state, next;
    
    always @(*) begin
        case(state)
            S1: next<= x ? S2:S1;
            S2: next<= x ? S5:S2;
            S3: next<= x ? S2:S3;
            S4: next<= x ? S3:S2;
            S5: next<= x ? S5:S4;
            default: next<= 'x;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset)
            state<=S1;
        else
            state<=next;
    end
    
    assign z = (state == 3'd3) || (state == 3'd4);
            

endmodule

Q3C_answer

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
    parameter S0=3'd0,S1=3'd1,S2=3'd2,S3=3'd3,S4=3'd4;
    reg [2:0] next;
    
    always @(*) begin
        case(y)
            S0: next <= x ? S1:S0;
            S1: next <= x ? S4:S1;
            S2: next <= x ? S1:S2;
            S3: next <= x ? S2:S1;
            S4: next <= x ? S4:S3;
            default: next<= 'x;
        endcase
    end
    
    assign Y0 = next[0];
    assign z  = (y == 3'd3) || (y == 3'd4);

endmodule