注意，不要在makefile语句后，加注释！
参考文章：makefile老是报“recipe for target xxx”错误，不妨先看看编码有空格
文章目录
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解决Makefile警告：覆盖目标xxx的配方
这篇文章将详细讨论如何解决在使用Makefile时遇到的常见问题：“warning: overriding recipe for target xxx”。在处理这个问题时，重要的是理解其原因，并知道如何通过改变我们的Makefile或工作流程来解决它。
1. 理解问题
1.1 Makefile简介
首先，了解一下Makefile。Makefile是一种构建自动化工具，通常用于编译和链接程序。Makefile文件描述了一个项目中的源文件以及如何从这些源文件构建可执行程序的规则。当运行“make”命令时，make工具会查找当前目录中的Makefile，并按照其中定义的规则构建目标。
# Makefile 示例
all: program
program: main.o util.o
gcc -o program main.o util.o
main.o: main.c
gcc -c main.c
util.o: util.c
gcc -c util.c
1.2 警告的来源
"overriding recipe for target xxx"这个警告是由于在同一个Makefile文件中，或者在包含的多个Makefile文件中，为同一个目标定义了多次配方（即构建规则）。例如：
# Makefile 示例
target:
echo "First definition"
target:
echo "Second definition"
在这个例子中，"target"被定义了两次，因此会出现警告。
2. 解决方法
2.1 检查并合并冗余的目标
在大型项目中，可能会有多个Makefile文件，如果不小心，可能会为同一个目标在不同的地方定义多次规则。最好的解决方法是审查所有的Makefile，确保每个目标只有一个定义。
例如，如果存在以下情况：
# Makefile A
target:
echo "Definition in Makefile A"
# Makefile B
target:
echo "Definition in Makefile B"
那么可以将它们合并成一个定义，如：
# Merged Makefile
target:
echo "Merged definition"
2.2 使用非递归Make
在某些情况下，可以通过避免在顶级Makefile中使用递归make来解决这个问题。这可以通过使用包含(include)语句来实现，该语句可以使一个Makefile包含其他Makefile的内容。
例如，如果有以下Makefile：
# Top-level Makefile
subdirs := dir1 dir2
.PHONY: all $(subdirs)
all: $(subdirs)
$(subdirs):
$(MAKE) -C $@
可以改写为：
# Top-level Makefile
include dir1/Makefile
include dir2/Makefile
3. 结论
处理“overriding recipe for target”的警告，需要理解其背后的原因：为同一个目标定义了多次配方。解决这个问题的关键在于确保每个目标只有一个定义，这可能需要检查和合并Makefile，或者改变构建工作流以避免使用递归make。
参考资料：
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