Vivado遇到的错误（一）

在Zynq7000上跑一个串口发送接收程序，因为没有用到rst_n的引脚，所以没有对其进行管脚约束，结果综合的时候报错，错误如下：
[DRC UCIO-1] Unconstrained Logical Port: 1 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_rst_n.

进行百度，说是要是不想管脚约束，就新建一个TCL文件，文件主要内容为：
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

在setting>>>Generate bit>>>TCl里面添加文件，重新编译即可。