基于vhdl的三人表决器（三种不同的描述方式）源码

ENTITY maj IS
   PORT(a,b,c : IN BIT; m : OUT BIT);
END maj;
--Dataflow style architecture
ARCHITECTURE concurrent OF maj IS
BEGIN
   --selected signal assignment statement (concurrent)
    WITH a&b&c SELECT
        m <= '1' WHEN "110"|"101"|"011"|"111",'0' WHEN OTHERS;
END concurrent;

--Structural style architecture
ARCHITECTURE structure OF maj IS

   --declare components used in architecture
   COMPONENT and2 PORT(in1, in2 : IN BIT; out1 : OUT BIT); 
   END COMPONENT;
   COMPONENT or3 PORT(in1, in2, in3 : IN BIT; out1 : OUT BIT); 
   END COMPONENT;
   --declare local signals
   SIGNAL w1, w2, w3 : BIT;

BEGIN
   --component instantiation statements. 
   --ports of component are mapped to signals 
   --within architecture by position.
   gate1 : and2 PORT MAP (a, b, w1);
   gate2 : and2 PORT MAP (b, c, w2);      
   gate3 : and2 PORT MAP (a, c, w3);      
   gate4 : or3 PORT MAP (w1, w2, w3, m);      
END structure;

--Behavioural style architecture using a look-up table
ARCHITECTURE using_table OF maj IS
BEGIN
   PROCESS(a,b,c)
      CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := "00010111";
      VARIABLE index : NATURAL;
   BEGIN
      index := 0; --index must be cleared each time process executes
      IF a = '1' THEN index := index + 1; END IF;
      IF b = '1' THEN index := index + 2; END IF;
      IF c = '1' THEN index := index + 4; END IF;
      m <= lookuptable(index);
   END PROCESS;
END using_table;