高速SAR ADC 关键技术研究和实现(一):自举开关

最近在学习高速ADC技术,从最简单的异步SAR开始,希望能够做出来一个完整的Pipeline SAR ADC 结构。

首先介绍高速ADC中的采样开关,由于采样开关作为ADC 与外部信号交互的部分,因此采样开关的速率决定了整个ADC的转换速率,传统的采样开关如图1所示,由传统的传输管和采样电容组成,在采样相位,时钟置高电平,NMOS导通,采样电容CS进行采样。在饱和区,MOS管的导通电阻为R=\frac{L}{\mu CW\left ( Vgs-Vth \right )},此时导通电阻保持不变,但是在线性区,导通电阻为R=\frac{1}{\mu C\left ( \frac{W}{L} \right )\left ( Vdd-Vin-Vth \right )},此时,导通电阻的阻值会随着输入电压的变化而变化,这样会造成ADC的转换精度下降,因此,实际应用中,我们希望减小输入对采样开关导通电阻的影响,为此本次设计采用自举开关代替传统的采样电路。

图1 传统的采样开关

自举开关的原理如图2 所示,与传统的采样开关相比,自举开关多了一个自举电容,在未采样阶段,电源先给自举电容充电;采样阶段充电端断开,自举电容的下级板接在NMOS的源端,这样栅源电压Vgs恒为Vdd,NMOS一直工作在饱和区,导通电阻值不变。

图2 自举开关原理 

根据以上原理,本次设计提出的自举开关电路结构如图3所示,当电路处于保持阶段,CLK=1,此时电容被充电至VDD*CS,当采样阶段,采样管M1的栅端电压被置为VDD+VIN,这样,电路在内部就完成了使采样管在采样阶段栅源电压不变,从而保证导通电阻阻值不变,提高了ADC的线性度和精度。

 图3 高速ADC自举开关

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This dissertation proposes three circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed and achieve excellent energy efficiency. The proposed techniques and chip measurement results are sketched as follows: The first technique is a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total sampling capacitance are reduced by about 81.3% and 50%, respectively. A 10-bit, 50-MS/s SAR ADC with the proposed monotonic capacitor switching procedure is implemented in a 0.13-μm 1P8M CMOS technology. The prototype ADC consumes 0.92 mW from a 1.2-V supply, and the effective number of bit (ENOB) is 8.48 bits. The resulting figure of merit (FOM) is 52 fJ/conversion-step. However, the signal-dependent offset caused by the variation of the input common-mode voltage degrades the linearity of ADC. We proposed an improved comparator design to avoid the linearity degradation. Besides, to avoid a clock signal with frequency higher than sampling rate, we used an asynchronous control circuit to internally generate the necessary control signals. The revised prototype is also implemented in a 0.13-μm 1P8M CMOS technology. It consumes 0.826 mW from a 1.2-V supply and achieves an ENOB of 9.18 bits. The resultant FOM is 29 fJ/conversion-step.

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