Verilog四输入排序电路代码

设计代码

`timescale 1ns / 1ps
module Test1342(clk,a,b,c,d,out1,out2,out3,out4);
input clk;
input [3:0] a,b,c,d;
output [3:0] out1,out2,out3,out4;
reg [3:0] out1,out2,out3,out4;
reg [3:0] temp1,temp2,temp3,temp4;

always @(posedge clk)
   begin
      {temp1,temp2,temp3,temp4}={a,b,c,d};
      sort(temp1,temp3);
      sort(temp2,temp4);
      sort(temp1,temp2);
      sort(temp3,temp4);
      sort(temp2,temp3);
      {out1,out2,out3,out4}={temp1,temp2,temp3,temp4};
   end
task sort;
inout [3:0] m,n;
reg [3:0] temp;

if(m>n) 
   begin
      temp=m;
      m=n;
      n=temp;
   end
endtask   

endmodule

测试代码

`timescale 1ns / 1ps
module Test1351;
reg clk;
reg [3:0] a,b,c,d;
wire [3:0] out1,out2,out3,out4;
always begin
   #10 clk=1;
   #10clk=0;
end

initial begin
   clk=0;
   a=0;
   b=0;
   c=0;
   d=0;
   #100;
   a=5;
   b=4;
   c=3;
   d=2;
   #100;
   a=8;
   b=9;
   c=6;
   d=1;
   #100;
   a=5;
   b=4;
   c=6;
   d=8;
   #100;
   a=1;
   b=2;
   c=3;
   d=4;
end

Test1342 s1(.clk(clk),
            .a(a),
            .b(b),
            .c(c),
            .d(d),
            .out1(out1),
            .out2(out2),
            .out3(out3),
            .out4(out4));
endmodule

代码逻辑比较简单，测试代码已经在VIVADO 2019版本上运行仿真成功。