HDMI2.1 Retimer 12Gbps（FRL）Transmitter

IT66319 is a single-in, single-out HDMI retiming buffer that supports a signaling rate of up to 12 Gbps per channel. 
IT66319是一款单进单出HDMI重定时缓冲器，支持每通道高达12 Gbps的信号速率。

It is compliant with the latest HDMI 2.1a specification and backward compatible with HDMI 1.4x/2.0x specification. 
它符合最新的HDMI 2.1a规范，并向后兼容HDMI 1.4x/2.0x规范。

With 48-Gbps/4-channel capability, IT66319 can support extra-high resolution content stream, such as the ultra-HD 8K x 4K format. 
凭借48gbps /4通道的能力，IT66319可以支持超高分辨率内容流，例如超高清8K x 4K格式。

At extremely high data rate like that, signal quality drops significantly with extended board trace or cable length, making an additional retiming buffer necessary in many systems.
在这样的极高数据速率下，信号质量会随着电路板走线或电缆长度的延长而显著下降，这使得在许多系统中需要额外的重定时缓冲区。

The IT66319 supports both the traditional TMDS signal as defined in the HDMI 1.4x/2.0x specification and the FRL signal developed in the HDMI 2.1x specification. 
IT66319既支持HDMI 1.4x/2.0x规范中定义的传统TMDS信号，也支持HDMI 2.1x规范中开发的FRL信号。

It detects which type of the signal is being transmitted from the source, and switches to appropriate communication mode automatically. 
它检测从源传输的信号类型，并自动切换到适当的通信模式。

Moreover, video contents with features such as VRR, FVA, or DSC compression enabled as defined in the HDMI 2.1a are fully supported. 
此外，完全支持HDMI 2.1a中定义的VRR, FVA或DSC压缩等功能的视频内容。

The insertion of the re-timer on the system is essentially transparent to both the source and the sink devices.
在系统上插入重计时器对源设备和接收设备基本上是透明的。

The IT66319 equalizes incoming TMDS/FRL signal to optimal and outputs retimed data to downstream sinks. 
IT66319将输入的TMDS/FRL信号均衡到最佳状态，并将重新定时的数据输出到下游sink。

The highly acclaimed equalization technology of ITE TECH. INC. provides support of long or low-quality on-board PCB trace at even the highest speeds. 
ITE TECH. INC.广受好评的均衡技术即使在最高速度下也能支持长或低质量的板载PCB走线。

Input terminations of the TMDS/FRL inputs and output terminations and current levels are both detachable and programmable.
TMDS/FRL的输入端和输出端以及电流电平都是可拆卸和可编程的。

An active DDC buffer is equipped in IT66319 to completely isolate downstream DDC loading from upstream source, while communication on the DDC bus not affected, including backward Read Request feature defined in HDMI 2.0x.
IT66319中配备了一个有源DDC缓冲器，可以完全隔离下游DDC负载与上游源，同时不影响DDC总线上的通信，包括HDMI 2.0x中定义的向后读请求功能。

With embedded MCU and Flash, IT66319 can be easily programmed through the ISP or DDC pins. 
IT66319具有嵌入式MCU和Flash，可以通过ISP或DDC引脚轻松编程。

The integrated MCU controls IT66319 by itself, thus reducing customer development and programming efforts. 
集成的MCU自行控制IT66319，从而减少了客户的开发和编程工作。

Furthermore, the IT66319 employs no crystal for FRL signal regeneration. 
此外，IT66319不采用晶体进行频响信号再生。

The overall BOM cost and board size could be minimized with least external components required.
总体BOM成本和电路板尺寸可以最小化，所需的外部组件最少。