这道题的有限状态机部分和上一题相同,主要部分是输出数据的设计
一开始我就想到用移位寄存器,这个题和前面有道题的数据顺序是相反的,in作为输入,最早输入的数据是最低位所以实现起来也是右移寄存器。
out <= {in, out[7:1]};
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter IDLE = 4'd0, START = 4'd1, DATA = 4'd2, STOP = 4'd3, ERROR = 4'd4;
reg[2:0] STATE, NEXT_STATE;
reg[2:0]counter1;
reg[7:0]out;
// Use FSM from Fsm_serial
//FSM PART
always @ (*)begin
case(STATE)
IDLE:NEXT_STATE = in ? IDLE : START;
START:NEXT_STATE = DATA;
DATA:NEXT_STATE = (counter1 == 4'd7) ? (in ? STOP : ERROR) : DATA;
S