See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)
State | Next state | Output | |
---|---|---|---|
in=0 | in=1 | ||
A | A | B | 0 |
B | C | B | 0 |
C | A | D | 0 |
D | C | B | 1 |
Module Declaration
module top_module( input clk, input in, input reset, output out);
自己写的代码:
module top_module(
input clk,
input in,
input reset,
output out);
//采用同步置位reset
reg[3:0] state;
parameter A = 0, //0001
B = 1, //0010
C = 2, //0100
D = 3; //1000
// State transition logic
always @(posedge clk) begin
if(reset)begin
state <= 4'b0001;
end
else begin
state[A] <= state[A]&(~in)|state[C]&(~in);
state[B] <= state[A]&in | state[B]&in |state[D]∈
state[C] <= state[B]&(~in) | state[D]&(~in);
state[D] <= state[C]∈
end
end
// State flip-flops with synchronous reset
// Output logic
assign out = state[D];
endmodule
标准的写法是在always @(posedge clk)模块中写
if(reset)begin
state <= 4'b0001;
end
else begin
state <= nextstate;
end
通过组合逻辑对nextstate的状态进行改变
下面是标准的代码:
module top_module(
input clk,
input in,
input reset,
output out);
//采用同步置位reset
reg[3:0] state,nextstate;
parameter A = 0, //0001
B = 1, //0010
C = 2, //0100
D = 3; //1000
// State transition logic
always @(*)begin
nextstate[A] <= state[A]&(~in)|state[C]&(~in);
nextstate[B] <= state[A]&in | state[B]&in |state[D]∈
nextstate[C] <= state[B]&(~in) | state[D]&(~in);
nextstate[D] <= state[C]∈
end
// State flip-flops with synchronous reset
always @(posedge clk) begin
if(reset)begin
state <= 4'b0001;
end
else begin
state <= nextstate;
end
end
// Output logic
assign out = state[D];
endmodule