HDLBits练习——Fsm3s

See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)

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前言

三个输入，包括一个时钟clk，一个高电平有效的同步置位信号reset，一个输入信号in；一个输出信号out。

代码

module top_module(
    input clk,
    input in,
    input reset,
    output out);