Vivado 之 Nexys4 DDR 实验

Vivado 之 Nexys4 DDR

第一关代码

module lab1(
    input[1:0]SW,
    output [3:0]LED);
    assign LED[0] = SW[0];
    assign LED[1]= !SW[1];
    assign LED[2] = SW[0]|SW[1];
    assign LED[3] = SW[0] & SW[1];
endmodule

module lab_1();
    reg [1:0]SW;
    wire [3:0]LED;
    
    lab1 uut(
    .SW(SW),
    .LED(LED));
    initial
    SW = 0;
    always
    begin
    #50;
    SW =2'b00;
    #50;
    SW =2'b01;
    #50;
    SW =2'b10;
    #50;
    SW =2'b11;
    end

endmodule

第二关代码

module pc_reg(

    input wire  clk,
    input wire  rst,
    output reg[5:0] pc,
    output reg  ce
);
always @ (posedge clk) begin
    if (ce == 1'b0) begin
        pc <=6'h00;
    end else begin
        pc<=pc + 1'b1;
    end
end
always @ (posedge clk) begin
    if (rst == 1'b1) begin
        ce <= 1'b0;
    end else begin
        ce <= 1'b1;
    end
end
endmodule

module rom(
    input wire  ce,
    input wire[5:0] addr,
    output reg[31:0]   inst
);
    reg [31:0]  rom[63:0];
initial $readmemh ( "rom.data" , rom );always @ (*) begin
    if (ce == 1'b0) begin
        inst <=32'h0;
    end else begin
        inst <=rom[addr];
    end
end
endmodule

module inst_fetch(
    input wire  clk,
    input wire  rst,
    output wire[31:0]    inst_o
);
    wire[5:0] pc;
    wire rom_ce;
    pc_reg pc_reg0(
    .clk(clk),
    .rst(rst),
    .pc(pc),
    .ce(rom_ce)
);
rom rom0 (
    .ce( rom_ce) ,
    .addr(pc),
    .inst(inst_o));
endmodule

`timescale 1ns/1ps
module inst_fetch_tb;
reg CLOCK_50;
reg rst;
wire[31:0]  inst;
initial begin
CLOCK_50= 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end

initial begin
rst = 1'b1;
#195 rst= 1'b0;
#1000 $stop;
end

inst_fetch inst_fetch0(
    .clk(CLOCK_50),
    .rst(rst),
    .inst_o(inst)
) ;
endmodule

第三关代码

`define RstEnable   1'b1
`define RstDisable  1'b0
`define ZeroWord    32'h00000000
`define WriteEnable  1'b1
`define WriteDisable    1'b0
`define ReadEnable  1'b1
`define ReadDisable 1'b0
`define AluopBus 7:0
`define AluselBus   2:0
`define InstValid   1'b0
`define InstInvalid 1'b1
`define True_v  1'b1
`define False_v 1'b0
`define ChipEnable  1'b1
`define ChipDisable 1'b0

`define EXE_ORI 3'b110
`define EXE_NOP 6'b000000
`define EXE_OR_OP   7'b0010011
`define EXE_NOP_OP  8'b00000000
`define ALU_ORI_OP  8'b00000001

`define EXE_RES_L0GIC   3'b001
`define EXE_RES_NOP 3'b000

`define InstAddrBus 31:0
`define InstBus 31:0
`define InstMemNum  131071
`define InstMemNumLog2  17

`define RegAddrBus  4:0
`define RegBus  31:0
`define RegWidth    32
`define DoubleRegWidth  64
`define DoubleRegBus    63:0
`define RegNum  32
`define RegNumLog2  5
`define NOPRegAddr  5'b00000

include "defines. v"
module pc_reg(
    input wire  clk,
    input wire  rst,
    output reg[`InstAddrBus]    pc,
    output reg  ce
    );
always @ (posedge clk) begin
if (ce == `ChipDisable) begin
pc<=32'h00000000;
end else begin
pc <= pc + 4'h4;
end
end
always @ (posedge clk) begin
if (rst == `RstEnable) begin
ce <= `ChipDisable;
end else begin
ce <= `ChipEnable;
end
end
endmodule

include "defines.v"
module if_id (
    input wire   clk,
    input wire   rst,
    input wire[`InstAddrBus]if_pc ,
    input wire[`InstBus ] if_inst,
    output reg[`InstAddrBus ] id_pc,
    output reg[`InstBus]   id_inst\
    );
always @ (posedge clk) begin
if (rst == RstEnable) begin
id_pc <= `ZeroWord;
id_inst <= `Zeroword;

end else begin
id_pc <= if_pc;

id_inst <= if_inst;
end
end
endmodule

第四关代码

module regfile(
input wire  clk,
input wire  rst,

input wire  we,
input wire[`RegAddrBus]  waddr,
input wire[`RegBus] wdata,

input wire  re1,
input wire  [`RegAddrBus]   raddr1,
output reg [`RegBus]    rdata1,

input wire  re2,
inputwire[`RegAddrBus]  raddr2,
output reg [`RegBus]    rdata2
);

reg[`RegBus]    regs[0:`RegNum-1];
always @ (posedge clk) begin
if (rst = `RstDisable) begin
if((we ==`WriteEnable) && (waddr != `RegNumLog2'h0)) begin
regs[waddr] <=wdata;
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
rdata1 <= `ZeroWord;
end else if( raddr1 = `RegNumLog2'h0) begin
rdata1 <= `ZeroWord ;
end else if((raddr1 == waddr)&& (we = `WriteEnable) && (re1 ==`ReadEnable)) begin
rdata1 <= wdata ;
end else if(re1 ==`ReadEnable) begin rdata1 <= regs [raddr1] ;
end else begin
    rdata1 <= 'ZeroWord;
    end
end
always @ (*) begin
if(rst == `RstEnable) begin
rdata2 <= `ZeroWord;
end else if( raddr2 = `RegNumLog2'h0) begin
rdata2 <= `ZeroWord ;
end else if((raddr2 == waddr)&& (we = `WriteEnable) && (re2 ==`ReadEnable)) begin
rdata2 <= wdata ;
end else if(re2 ==`ReadEnable) begin rdata2 <= regs [raddr2] ;
end else begin
    rdata2 <= 'ZeroWord;
    end
end
endmodule

include "defines. v"
module id(
input wire  rst,
input wire[`InstAddrBus]    pc_i,
input wire[`InstBus]    inst_i,

input wire[`RegBus] reg1_data_i,
input wire[`RegBusj reg2_data_i,

output reg  reg1_read_o,
output reg  reg2_read_o,
output reg[`RegAdd rBus]    reg1_addr_o,
output reg[`RegAdd rBus]    reg2_addr_o,

output reg [`AluOpBus]  aluop_o,
output reg[`AluselBus]  alusel_o
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg  wreg_o
);

wire[6:0]opcode = inst_i[6:0];
wire[4:0]rd= inst_i[11:7];
wire[2:0]funct3 = inst_i[14:12];
wire[4:0]rs1=inst_i[19:15];

reg [`RegBus] imm;

reg instvalid;

always @ (*) begin
if ( rst -`RstEnable) begin
aluop_o
=`EXE_NOP__OP;
alusel_o
<=`EXE_RES_NOP;
wd_o
`NOPRegAddr;
wreg_o
`writeDisable;
instvalid
<`InstValid;
reg1_read_o
<=1 'b0;
reg2_read_o
<=1 'b0;
reg1_addr_o
`NOPRegAddr ;
reg2_addr_o
=`NOPRegAddr;
imm
<32 ' h0 ;
end else if (opcode ==‘EXE_OR_OP && funct3 E=`EXE_ORI) begin
wreg_o
=`writeEnable;
aluop_o
`ALU_ORI__OP;
alusel_o
`EXE_RES_LOGIC;
reg1_read_o
<1 'b1;
reg2_read_o
<= 1 'b0 ;
reg1_addr_o
=rs1;
reg2_addr_o
=rd ;
wd_o
=rd;
instvalid
`InstValid;
imm
=ii20{inst_i[31]}},inst_i[31:20]};
end
else begin
aluop_o
`EXE_NOP_OP;
alusel_o
`EXE_RES_NOP;
wreg_o
= writeDisable;
instvalid
`InstValid ;
reg1_read_o
<=1'b0;
reg2_read_o
< 1'b0;
reg1_addr_o
 rs1;
reg2_addr_o
 rd;
wd_o
rd ;
imm
<= `zeroword;
end