HDLBits FSM Q2a-b

q2afsm

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
	wire r1,r2,r3,g1,g2,g3;
    assign r1 = r[1];
    assign r2 = r[2];
    assign r3 = r[3];
   
    parameter A = 3'd1,B = 3'd2,C = 3'd3,D = 3'd4;
    
    reg [2:0] cs,ns;
    
    always@(posedge clk)
        begin
            if(!resetn)
                cs <= A;
            else
                cs <= ns;
        end
    always@(*)
        begin
            case(cs)
                A: begin
                    if(r1)
                        ns = B;
                    else if(~r1 & r2)
                        ns = C;
                    else if(~r1 & ~r2 & r3)
                        ns = D;
                    else 
                        ns = A;
                end
                B: ns = r1 ? B : A;
                C: ns = r2 ? C : A;
                D: ns = r3 ? D : A;
                default: ns = A;
            endcase
        end
    assign g[1] = cs==B;
    assign g[2] = cs==C;
    assign g[3] = cs==D;
endmodule

q2bfsm

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter A = 4'd0, F_out = 4'd1, B = 4'd2, C = 4'd3, D = 4'd4;
    parameter E = 4'd5, F = 4'd6, all_1 = 4'd7,all_0 = 4'd8;
    reg [3:0] cs,ns;

    always@(posedge clk)
        begin
            if(!resetn)
                cs <= A;
            else
                cs <= ns;
        end
    always@(*)
        begin
            case(cs)
                A: ns = F_out;
                F_out: ns = B;
                B: ns = x ? C : B;  //检测x的初状态，0
                C: ns = x ? C : D;
                D: ns = x ? E : B;
                E: ns = y ? all_1 : F;
                F: ns = y ? all_1 : all_0;
                all_1: ns = all_1;
                all_0: ns = all_0;
                default: ns = A;
            endcase
        end
    
    assign f = cs==F_out;
    assign g = cs==all_1 || cs==E || cs==F;

endmodule