module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter A=0,B=1;
reg state,next_state;
reg z_next;
reg [1:0]count,next_count,next_ocount,ocount;//count 用来对B的周期计数,ocount用于计算1的总个数
always@(*)begin
next_state=state;
z_next=z;
next_ocount=ocount;
next_count=count;
if(reset)begin
next_state=A;
next_ocount=0;
z_next=0;
next_count=0;
end
else begin
case(state)
A:begin
if(s)begin
next_state=B;
next_count=0;
next_ocount=0;
end
end
B:begin
z_next=0;
next_count=count+1;
if(w)begin
next_ocount=ocount+1;
end
if(count==2)begin
next_count=0;
if(next_ocount==2)begin
z_next=1;
end
next_ocount=0;
end
end
endcase
end
end
always@(posedge clk)begin
state=next_state;
count=next_count;
ocount=next_ocount;
z=z_next;
end
endmodule
结果