HDLbits—Exams/2014 q3fsm
当s为0时,进入B状态,然后会检查w的值,如果在接下来的三个周期中w值有两个周期都为1,那么z输出1,否则z输出0。注意,这里隐含的条件是不重叠检测,意味着每三个周期检查一次,周期与周期之间不重叠。一开始没看清楚以为会是重叠检测,结果没这么复杂。习惯输出用时序逻辑,所以考虑的是在计数时钟counter == 2时的2种情况,看了别人的使用assign也挺方便的。
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter S0 = 1'd0,S1 = 1'd1;//S0状态a,S1正常计数情况
reg state,next_state;
reg [1:0] clk_counter,w_counter;//clk_counter 计数3个时钟周期,w_counter计数w=1 计数2次的情况;
always@(posedge clk)begin
if(reset)
state = S0;
else
state = next_state;
end
//计数器模块
always@(posedge clk)begin
if(reset)begin
clk_counter <= 0;
w_counter <= 0;
end
else begin
//clk_counter 计数3个时钟周期
if(state == S1)begin
if(clk_counter == 2'd2)begin
clk_counter <= 0;
w_counter <= 0;
end
else begin
clk_counter <= clk_counter + 1;
if(w == 1)begin
w_counter <= w_counter + 1;
end
end
end//state == S1
end//else
end//always
//次态转移模块
always@(*)begin
case(state)
S0:begin
if(s)begin
next_state = S1;
end
else begin
next_state = S0;
end
end
S1:begin
next_state = S1;
end
default:next_state = S0;
endcase
end
//根据图中内容可知,会存在2种情况,3个周期结束后,1,2周期w拉高,1,3周期w拉高
always@(posedge clk)begin
if(reset)
z = 0;
else if((clk_counter == 2'd2 && w_counter == 1 && w == 1)|(clk_counter == 2'd2 && w_counter == 2 && w == 0))
z = 1;
else
z = 0;
end
endmodule