https://hdlbits.01xz.net/wiki/Exams/2014_q3fsm
error info:
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter A=0,B=1;
reg state,next;
reg[2:0]d;
parameter S0=0,S1=1,S2=2,S3=3;
reg [1:0]cs,ns;
always @(*)
begin
case(state)
A:next=s?B:A;
B:next = B;
default next = A;
endcase
end
always @(posedge clk)
begin
if (reset)
state<= A;
else
state<= next;
end
always @(*)
begin
case(cs)
S0:ns=S1;
S1:ns=S2;
S2:ns=S3;
S3:ns=S0;
default: ns=S0;
endcase
end
always @ (posedge clk)
begin
cs<=ns;
if(state==B)
begin
d<={d[1:0],w};
end
end
assign z=(state==B)&&(cs==S0)&&((d==3'b111)|(d==3'b110)|(d==3'b101)|(d==3'b011));
endmodule