VHDL 测试文件模板

entity testbench is

end testbench;

architecture Behavioral of testbench is
component fredevider3 is
port(
    clock:in std_logic;

    reset:in std_logic;
    clkout:out std_logic
);
end component fredevider3;

constant clk_period:time:=100 ns;

signal reset:std_logic:='0';
signal clk1: std_logic:='0';
signal clk2: std_logic;

begin
u1: fredevider3
port map(
    clock=>clk1,

    reset=>reset,
    clkout=>clk2
);

--产生时钟信号

process
begin
clk1<='1';
wait for clk_period/2;
clk1<='0';
wait for clk_period/2;
end process;

--产生reset信号

process

begin

wait for 100ns;

reset<='1';

wait for 100ns;

reset<='0';

wait;

end process;

end Behavioral;