参考:
xilinx 除法ip核(divider) 不同模式结果和资源对比(VHDL&ISE)_ise除法器ip核-CSDN博客
数字信号处理-04- FPGA常用运算模块-除法器(二)-阿里云开发者社区 (aliyun.com)
【FPGA】:ip核--Divider(除法器)_除法器ip核-CSDN博客
数字信号处理-04- FPGA常用运算模块-除法器_tlast-CSDN博客
目的:还原出真实的白色
色温的概念和示例:
涉及的资源:除法器、乘法器
除法器基本介绍
LUTMult.
LUTMult
. A simple lookup estimate of the reciprocal of the divisor followed by a
multiplier. Only remainder output type is supported because of the bias required in the
reciprocal estimate. This bias would introduce an offset (error) if used to create a
fractional output. This is recommended for operand widths less than or equal to 12 bits.
This implementation uses DSP slices, block RAM and a small amount of FPGA logic
primitives (registers and LUTs). For operand widths where either Radix2 or the LUTMult
options are possible, the LUTMult solution offers a solution using fewer FPGA logic
resources because of the use of DSP and block RAM primitives.
除数的倒数和乘数的简单查找估计。由于倒数估计中需要偏差,因此仅支持余数输出类型。如果用于创建小数输出,此偏差会引入偏移(误差)。对于小于或等于 12 位的操作数宽度,建议这样做。该实现使用 DSP Slice、Block RAM 和少量 FPGA 逻辑原语(寄存器和 LUT)。对于可以使用 Radix2 或 LUTMult 选项的操作数宽度,LUTMult 解决方案提供了一种使用更少 FPGA 逻辑资源的解决方案,因为使用了 DSP 和 Block RAM 原语。
Radix-2.
Radix-2.
Radix-2 non-restoring integer division using integer operands, allowing either
a fractional or an integer remainder to be generated. This is recommended for operand
widths less than around 16 bits or for applications requiring high throughput. The
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implementation uses FPGA logic primitives (registers and LUTs). The Radix2 solution does not use DSP or