VHDL并行语句（Concurrent Statements）

VHDL并行语句（Concurrent Statements）

并行语句和其他并行语句同步执行。以为为并行语句：
Concurrent statements are concurrent with respect to all other such statements. The following are concurrent statements:

• 进程 Process
• 块 Block
• 实例 Instantiation
• 断言 Assert
• 生成 Generate
• 过程调用 Procedure call
• 信号赋值 Signal assignment

进程（Process）

进程语句定义了一些独立的连续进程，来完成设计的部分行为功能。
A process statement defines an independent sequential process representing the behavior of some portion of the design.

语法（Syntax）

[ 标号: ] [ postponed ] process [ ( 敏感列表 ) ] [ is ] 
  进程声明 
begin 
  顺序语句 
end [ postponed ] process [ 标号 ] ;

[ label: ] [ postponed ] process [ ( sensitivity_list ) ] [ is ] 
  process_declarations 
begin 
  sequential_statements 
end [ postponed ] process [ label ] ;

说明（Description）

进程语句实现设计的一部分行为功能。他包含一些用户定义的顺序语句。
The process statement represents the behavior of some portion of the design. It consists of the sequential statements whose execution is made in order defined by the user.
进程声明部分定义的项仅对进程可见。声明部分可以包含以下几种声明：子程序，类型，子类型，常量，变量，文件，断言，属性，使用实例和组声明。不允许在进程里声明信号或者共享变量。
The process declarative part defines items that are only visible within that process. The declarative part may contain declarations of: subprograms, types, subtypes, constants, variables, files, aliases, attributes, use clauses and group declarations. It is not allowed to declare signals or shared variables inside processes.
Loop中进程语句的执行顺序为自顶至下。当执行完最后一条语句，将继续执行第一条语句。进程可以使用wait语句来挂起和继续。当进程的下一条语句是wait语句时，进程暂停执行直到满足wait条件。
A process is a loop in which the statements are executed from top to bottom. After the last statement is executed, execution will continue with the first statement. The loop can be suspended and resumed with wait statements. When the next statement to be executed is a wait statement, the process suspends its execution until the wait condition is met.
敏感列表是可选项，包含一些进程敏感信号列表。敏感信号列表中的信号值改变将唤醒暂停的进程。敏感信号列表等同于在进程底部的wait敏感列表语句。
The sensitivity list is optional and contains a list of signals to which the process is sensitive. A change of a value of one of these signals causes the suspended process to resume. A sensitivity list is equivalent to wait on sensitivity_list at the end of the process.
在仿真尾部，当所有其他进程完成后将运行一个延迟（postponed）进程。他们的主要应用是基于信号的稳定状态（steady-state）值来实现时间（timing）或者函数（functional）检测。
A postponed process runs when all other processes have completed, at the end of a simulation. Their main use is to perform timing or functional checks, based on the ‘steady-state’ values of signals.

例程（Example）

Counter: process (Clk, Reset)
  variable Increment: integer := 1;
begin 
  if Reset = '0' then
    Q <=  (others => '0');
  elsif rising_edge(Clk) then
    if Count = '1' then 
      Q <= Q + Increment;
    end if; 
  end if; 
end process;

注释（Notes）

• 不允许在同一进程中同时使用wait语句和敏感列表。

• It is not allowed to use wait statements and sensitivity list in the
  same process.

• 有敏感列表的进程叫做过程，过程中不允许包含wait语句。

• If a process with a sensitivity list calls a procedure, then the
  procedure cannot contain a wait statement.

敏感列表（Sensitivity List）
信号列表来触发进程继续执行。
A list of signals that triggers a process to resume.

语法（Syntax）

( signal_name, ... ) 

说明（Description）

敏感列表等同于wait语句。敏感列表中的一个（或多个）信号事件将使进程继续。当一个进程有敏感列表，进程将在执行完最后一条顺序语句后停止执行，直到敏感信号列表中的信号事件发生。
The sensitivity list is equivalent to the wait on statement. An event on one (or more) of the signals listed in the sensitivity list will make the process to resume. When a process has a sensitivity list, then that process will always stop executing at the end of the sequential statements, and wait on an event on one (or more) of the signals listed in the sensitivity list.
仅可读的静态信号名才能出现在进程的敏感列表中。
Only static signal names, for which reading is permitted, may appear in the sensitivity list of a process.

例程（Example）

Dff : process (Clk, Reset) 
begin 
  ...
end process;

注释（Notes）

• 有敏感列表的进程不能有wait语句。
• A process with a sensitivity list may not contain any explicit wait
  statements.

块（Block）

块语句用来组织结构体的并行语句。
The block statement is used to group together concurrent statements in an architecture.

语法（Syntax）

快标号: block [ ( 保护条件 ) ] [ is ] 
  [ generic; [ 类属映射; ] ] 
  [ port; [ 端口映射; ] ] 
  [ 块声明 ] 
begin 
  并行语句 
end block [ 块标号 ]; 

block_label: block [ ( guard_condition ) ] [ is ] 
  [ generic; [ generic_map; ] ] 
  [ port; [ port_map; ] ] 
  [ block_declarations ] 
begin 
  concurrent_statements 
end block [ block_label ]; 

说明（Description）

块语句在结构体中组织并行语句。块应用主要有两个应用：提高代码可读性和来通过使用guarded表达式来屏蔽一些信用。
The block statement groups concurrent statements in an architecture. The two main purposes for using blocks are: improve readability of the specification and to disable some signals by using the guarded expression (see Guarded).
块语句仅用于提高组织性。块的使用不会影响仿真模式的执行。
The block statement is organisational only - the use of a block does not directly affect the execution of a simulation model.
端口映射和类属映射语句用来将块外部声明的对象和快内声明的对象分别来对应。然而，这种结构只有一点实用价值。
The purpose of the port map and generic map statements is to map signals and other objects declared outside of the block into the ports and generic parameters that have been declared inside of the block, respectively. This construct, however, has only a small practical importance.
块内声明的对象不对块外部可见。
The block declarations are local to the block and are not visible outside it.

例程（Example）

signal P, Q, R: std_logic;
...
level1: block
  port(A, B: in std_logic;
       C: out std_logic);
  port map(A => P, B => Q, C => R); 
begin 
  C <= A and B;
end block level1;

注释（Notes）

• 没有必要去学习块和相关语法的使用。通常使用进程语句来代替他。
• It is not necessary to learn and use blocks and related syntax (such as guarded signal assignments). It is generally more efficient for simulation to use processes instead.
• 不建议在non-VITAL设计中使用块。
• It is strongly recommended not to use blocks in non-VITAL designs.
• VITAL规格需要使用块。
• VITAL specifications require the use of blocks.

Guarded

块中一个有关布尔型值的表达式用来控制保护信号的赋值。保护表达式定义了一个隐式信号GUARD，用来控制确定语句的操作（通过连接或断开这些语句的驱动源）。
A Boolean-valued expression associated with a block statement that controls assignments to guarded signals within a block. A guard expression defines an implicit signal GUARD that may be used to control the operation of certain statements within the block (by connecting or disconnecting the drivers of those statements).

语法（Syntax）

block_signal <= guarded expression; 

说明（Description）

块语法的一个特性就是保护表达式。保护表达式是一个布尔型的逻辑表达式，无论有没有保护表达式出现，该表达式都会被隐式声明。
The characteristic feature of the block statement is the guard expression. It is a logical expression of the Boolean type, declared implicitly after the reserved word block whenever a guarded expression appears inside the block.
保护表达式隐式声明了一个名字为‘guarded’的信号。这个信号可以被块语句中的任何其他信号读取，但是不能被赋值表达式赋值。信号仅对本块可见。
The guard expression implies a signal named ‘guarded’ at the beginning of the block declaration part. This signal can be read as any other signal inside the block statement but no assignment statement can update it. This signal is visible only within the given block.
当给保护表达式右边的任何信号传递值时，表达式的值被计算并立即更新‘guarded’信号的值。如果表达式的值为真，则‘guarded’信号接收真值，否则接收假值。
Whenever a transaction occurs on any of the signals on the right hand side of the guard expression, the expression is evaluated and the ‘guarded’ signal is immediately updated. The ‘guarded’ signal takes on the True value when the value of the guard expression is True. Otherwise, ‘guarded’ takes on the False value.
‘guarded’信号也可以在块语句中特别声明。这种方法的优势是可是使用较复杂的算法来控制保护信号。在这种情况下，将使用一个单独的进程来驱动保护信号。
The ‘guarded’ signal may also be declared explicitly as a Boolean signal in the block statement. The advantage of this approach is that more complex (than a simple Boolean expression) algorithm to control the guard signal can be used. In particular, a separate process can drive the guard signal.
如果没有保护表达式和没有保护信号声明，则默认保护信号总是真。
If there is no guard expression and the guard signal is not declared explicitly, then by default the guard signal is always True.
保护信号用来控制所谓的保护并行信号赋值语句。每一个这种该语句在字符“<=”后添加一个保留字guarded。只有当保护信号为真时才给信号赋新值。否则，信号赋值语句将不更新给定信号的值。
The guard signal is used to control so called guarded concurrent signal assignment statements contained inside the block. Each such statement contains the reserved word guarded placed after the symbol “<=”. They assign a new value to the signal only when the guard signal is true. Otherwise, the signal assignment statement does not change the value of the given signal.

例程（Example）

RisingEdge : block (Clk'Event and Clk ='1') 
begin 
  Output1 <= guarded not Input1 after 15 ns; 
end block RisingEdge; 

Blk1 : block 
  signal SGuard: boolean := false; 
begin 
  Output1 <= guarded not Input1 after 15 ns; 
  Pr1: process 
  begin 
    SGuard <= true; 
  end process Pr1; 
end block Blk1;

注释（Note）

• 综合工具通常不支持保护型块。
• Guarded blocks are usually not supported for synthesis.

实例（Instantiation）

实例语句定义了一个设计实体中子元件。
An instantiation statement defines a sub-component of the design entity.

语法（Syntax）

实例标号: [ component ] 元件名 
  [ 类属映射 ] [ 端口映射 ];
实例标号: entity 实体名 [ ( 结构体名 ) ] 
  [ 类属映射 ] [ 端口映射 ];
实例标号: configuration 配置名 
  [ 类属映射 ] [ 端口映射 ]; 

instance_label: [ component ] component_name 
  [ generic map ] [ port map ];
instance_label: entity entity_name [ ( architecture_name ) ] 
  [ generic map ] [ port map ];
instance_label: configuration configuration_name 
  [ generic map ] [ port map ]; 

说明（Description）

实例是个并行语句，通过赋值一个底层的设计实体来定义一个多层级的设计。实例语句引用外部定义的子系统。
An instantiation is a concurrent statement which is used to define the design hierarchy by making a copy of a lower level design entity within an architecture. The instantiation statement introduces a subsystem declared elsewhere.
实例包含一个实例单元的引用和类属的实际值和端口。有三种形式的实例：
The instantiation contains a reference to the instantiated unit and actual values for generics and ports. There are three forms of instantiation:

• 元件实例化 instantiation of a component;
• 设计实体实例化 instantiation of a design entity;
• 配置实例化 instantiation of a configuration;

元件实例化表示已定义元件的关系单元。实例的元件名必须和已定义的元件名相同。调用实例化元件时要有类属的确切参数和端口。关系列表可以是位置对应的也可以是名字对应的。
Instantiation of a component introduces a relationship to a unit defined earlier as a component (see Component). The name of the instantiated component must match the name of the declared component. The instantiated component is called with the actual parameters for generics and ports. The association list can be either positional or named.
没有必要为了实例化元件而定一个元件：实体/结构体对可以直接被实例。在这种直接实例化里，实例化语句包含设计实体的名字，用于该设计实体的结构体名可有可无。
It is not necessary to define a component to instantiate it: the entity/architecture pair can be instantiated directly. In such a direct instantiation, the instantiation statement contains the design entity name and optionally the name of the architecture to be used for this design entity.

例程（Example）

u1: Nand4 port map(A, B, Q);
u2: entity work.Parity
  generic map(N => 8)
  port map(A => Data,
           Odd => ParityByte);

注释（Note）

• 实体，结构体或结构体必须在库中编译，才能被实例。但是元件实例可以在相对应的设计实体前编译。
• An entity, architecture or configuration must be compiled into a
  library before the corresponding instance can be compiled. However, an instance of a component can be compiled before the corresponding design entity has even be written.

生成（Generate）

描述功能中迭代或条件细化机制。
A mechanism for iterative or conditional elaboration of a portion of a description.

语法（Syntax）

标号: for 参数 in 范围 generate 
  [ 生成声明
begin ]  
   并行语句 
end generate [ 标号 ]; 

标号: if 条件 generate 
  [ 生成声明 
begin ] 
   并行语句 
end generate [ 标号 ]; 

label: for parameter in range generate 
  [ generate_declarations
begin ]  
   concurrent_statements 
end generate [ label ]; 

label: if condition generate 
  [ generate_declarations 
begin ] 
   concurrent_statements 
end generate [ label ]; 

说明（Description）

生成语句简化了设计结构描述。通常用来用一个元件说明并使用生成机制的重复来实现一组相同的元件。
The generate statement simplifies the description of regular design structures. Usually it is used to specify a group of identical components using just one component specification and repeating it using the generate mechanism.
生成语句包含三个主要部分：
A generate statement consists of three main parts:

• 生成机制（for机制或if机制）
• generation scheme (either for scheme or if scheme);
• 声明部分（子程序，类型，信号，常量，元件，属性，配置，文件和组的本地声明）

• declaration part (local declarations of subprograms, types, signals,
  constants, components, attributes, configurations, files and groups);

• 并行语句。

• concurrent statements.
  生成机制来指定如何来生成并行结构语句。有两种生成机制：for和if。
  The generation scheme specifies how the concurrent structure statement should be generated. There are two generation schemes available: for scheme and if scheme.
  For生成机制用来描述设计中规律性的结构。这种情况下，生成参数和其生成范围方式类似于顺序语句loop。
  The for generation scheme is used to describe regular structures in the design. In such a case, the generation parameter and its scope of values are generated in similar way as in the sequential loop statement.
  If生成机制用在那些在规律性结构中包含特例时。
  The if generation scheme is used when the regular structure contains some irregularities.

例程（Example）

G1: for I in 1 to N-1 generate 
  L: Blk port map (A(I), B(I+1)); 
end generate G1;

G2: if I = 3 generate 
  L: Blk port map (A(I+1), B(I+2)); 
end generate; 

注释（Notes）

• 每个生成语句都必须有标号。
• Each generate statement must have a label.
• 生成语句可能被分配网表资源。
• Generate statements can be nested.