VHDL库和包（Libraries and Packages）

最新推荐文章于 2024-08-10 21:29:54 发布

寸草心

最新推荐文章于 2024-08-10 21:29:54 发布

阅读量1.4w

点赞数 3

分类专栏： HDL

HDL 专栏收录该内容

30 篇文章 6 订阅

订阅专栏

VHDL库和包（Libraries and Packages）

设计库用来收集设计单元组成一个具有唯一名的域，可以被设计中多个源文件引用。设计单元是VHDL的主要组成部分。主设计单元是实体，包和配置。次设计单元是结构体和包主体。次设计单元依赖于和它相关联主设计单元的接口说明。
Design libraries are used to collect design units into uniquely-named areas that can be referenced from multiple source files in your design. Design units are the main components of a VHDL description. The primary design units are entities, packages and configurations. The secondary design units are architectures and package bodies. The secondary design units depend on the specification of their interface in a corresponding primary design unit.
包中包含通用的声明，如类型，常量，子程序等。包的内容可以用于整个设计或多各项目。
A package is a collection of commonly-used declarations such as types, constants, subprograms, etc. The contents of a package can be used throughout the design, or in multiple projects.
使用library和use子句来使库或包的内容在真个设计单元中可见。
The library and use clauses have to be used to make the contents of a library and package visible in a design unit.

包（Package）

包中包含的通用定义可以在整个VHDL或多个设计中共享使用。
A package contains common definitions that can be shared across a VHDL design or even multiple designs.

语法（Syntax）

package package_name is 
  package_declarations
end [ package ] [ package_name ];

说明（Description）

包用来组织各式各样的声明，使其可以被许多设计共享使用。包存储在库中。一个包被分为包声明（强制的）和包主体（可选）。
The package is a unit that groups various declarations, which can be shared among several designs. Packages are stored in libraries. A package is split into a package declaration (mandatory) and a package body (optional).
包存在的目的是用来声明共享的类型，子类型，常量，信号，文件，断言，元件，属性和组。一旦包被定义，他就可以在多个独立设计中使用。
The purpose of a package is to declare shareable types, subtypes, constants, signals, files, aliases, component, attributes and groups. Once a package is defined, it can be used in multiple independent designs.
输入使用了use子句，包中声明的项就可以在其他设计单元中可见。
Items declared in a package declaration are visible in other design units if the use clause is applied.

例程（Example）

library IEEE; 
use IEEE.std_logic_1164.all; 
package Utils is 
  constant Size: positive; 
  subtype Vec8 is std_logic_vector(7 downto 0);
  function Parity (V: Vec8) return std_logic; 
end Utils;

注释（Notes）

包声明可以包含子程序（函数或过程）声明；但子程序的主体不能出现在包声明中，必须在包主体内。
A package declaration may contain a subprogram (function or
procedure) declaration; the subprogram body is not allowed here and must appear in the package body.
包主体必须有一个包声明，如果声明中包含子程序声明或延迟常量。
A package body must accompany a package declaration if the
declaration contains subprogram declarations or deferred constants.
只有在包声明中定义的对象对外可见。
Only definitions placed in the package declaration are visible
outside the package.

包主体（Package Body）

包主体定义了包的子程序，以及包中定义的延迟常量值。
A package body defines the bodies of subprograms and the values of deferred constants defined in the package.

语法（Syntax）

package body package_name is 
  package_body_declarations 
end [ package body ] [ package_name ];

说明（Description）

包主体中包含完整的子程序主体，以及延迟常量值。其他声明也可以出现在包主体中，但是仅对包内部可用。
The package body includes complete definitions of subprogram body declarations as well as values of deferred constants declared in the corresponding package declarations. Other declarations (similar to those of package declaration) are also allowed here, but are visible only inside the package body.
包声明的延迟常量，可以在其完全声明前使用，仅当他是一个本地通用参数的默认值，本地端口或子程序的形式参数。
The deferred constant, which has been declared in a package declaration, may be used before its full declaration only in a default expression for a local generic parameter, local port or formal parameter of subprogram.

例程（Example）

package body Utils is 
  constant Size: positive := 16; 
  function Parity (V: Vec8) return std_logic is 
    variable B: std_logic := '0'; 
  begin 
    for I in V'Range loop 
      B:= B xor V(I); 
    end loop; 
    return B; 
  end Parity; 
end Utils;

注释（Notes）

除了延迟常数值和子程序主体外的声明对包主体外不可见。
Declarations other than values of deferred constants and subprogram bodies are not visible outside the package body.
每个包仅有一个主体。
Each package can have only one body.

库语句（Library）

Library子句在本地环境下，为设计库定义一个逻辑名。
A library clause defines logical names for design libraries in the host environment.

语法（Syntax）

library library_name, ... ;

说明（Description）

Library语句为设计库定义一个逻辑名，可以被设计单元使用。库是一个实现相关（implementation-dependent）的存储，为了便于预先分析设计单元。
The library clause defines the logical names of design libraries, which are used by the design units. A library is an implementation-dependent storage facility for previously analyzed design units.
VHDL库常被作为主机文件系统的一个路径来实现。库名对应文件路径。
A VHDL library is usually implemented as a directory in the host file system. The library name is mapped to the pathname of that directory by the VHDL tool.
有两个预定的库，被隐式使用：std和work。Std库包含包Standard和Textio。Work库是工作库，存储所有用户创建的分析的设计单元。所有用户指定的包都存储在工作库Work中。
There are two predefined libraries, which are used implicitly in every design: Std and Work. The Std library contains the packages Standard and Textio. The Work library is a working library, where all user-created and analyzed design units are stored. Also user-specified packages are stored in the working library Work.

例程（Example）

library IEEE;
library Work, IpCores;

注释（Notes）

在主设计单元中使用library语句指定的库，对其相关联的次级单元可见。
A library specified in a library clause of the primary design unit
(entity, configuration or package) is visible in each secondary unit
(architecture or package body) associated to it.
Std库没有必要特别指定。所有的库包被自动包含在每个设计单元中。
Library Std need not to be specified. Both library packages are
automatically included in every design unit.

使用语句（Use）

实现直接的声明可见。
Achieves direct visibility of declarations that are visible by selection.

语法（Syntax）

use 库名[ .包名 ].项名;

use library_name[ .package_name ].item_name;

说明（Description）

Use子句使库中定义的名字对其他VHDL代码区域可见。Use语句一般写在实体的头部，或者配置的头部。
The use clause makes names defined in a library directly visible within another region of the VHDL code. The use clause is typically written at the top of an entity (giving access to common definitions from a package) or at the top of a configuration (giving access to the entities and architectures in a library).

Use子句指定其指定的项名可见。如果要使包中所有的声明可见，可以使用保留字all。
The item_name specified in the use clause, specifies the item that will be visible. If a designer wants to have all declarations in a package visible, then the item_name should be substituted by the reserved word all.
Use子句对其紧跟的设计单元和次设计单元立即生效。如果文件包含多余一个设计单元，则每个设计单元必须有他自己的use语句。也就是说，文件中use语句表示全局性的。
The use clause is valid for the design unit immediately following it and for all secondary design units assigned to this design unit (if it is a primary design unit). If a file contains more than one design unit, then each design unit must have its own use clauses. In other words, use clauses are not global within a file.

例程（Example）

use IEEE.std_logic_1164.all; 
use WORK.ArithOp.Add;
use WORK.all

预定义包（Predefined Packages）

VHDL LRM提供了两个预定义包：Standard和TEXTIO
The VHDL LRM provides two predefined packages: Standard and TEXTIO.
包Std_logic_1164用来扩展VHDL为一个多值逻辑。基于包Std_logic_1164，包Numeric_std提供了数字数据的标准数据类型和运算符，
The package Std_logic_1164 has to be used to extend the VHDL into a multi-value logic. The package Numeric_std provides standard data types and operations for numeric data, based on the multi-value logic defined in Std_logic_1164.

标准包（Standard Package）

标准包预定义了数字类型，子类型和函数。
The Standard package predefines a number of types, subtypes, and functions.

说明（Description）

标准包是VHDL标准的一部分。包中定义了基本类型，子类型，函数，以及每种（子）类型的运算符。
The Standard package is part of the VHDL standard. This package contains definitions for basic types, subtypes, and functions, and the operators available for each of the (sub)types defined.
标准是隐式使用的，不需要用use子句来特别声明。
Use of the Standard package is implicitly assumed by every VHDL simulator and compiler and need not to be explicitly declared by the use clause.

package standard is 
  type boolean is (false,true); 
  type bit is ('0', '1'); 
  type character is (
    nul, soh, stx, etx, eot, enq, ack, bel, 
    bs,  ht,  lf,  vt,  ff,  cr,  so,  si, 
    dle, dc1, dc2, dc3, dc4, nak, syn, etb, 
    can, em,  sub, esc, fsp, gsp, rsp, usp, 

    ' ', '!', '"', '#', '$', '%', '&', ''', 
    '(', ')', '*', '+', ',', '-', '.', '/', 
    '0', '1', '2', '3', '4', '5', '6', '7', 
    '8', '9', ':', ';', '<', '=', '>', '?', 
    '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 
    'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 
    'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 
    'X', 'Y', 'Z', '[', '\', ']', '^', '_', 
    '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 
    'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 
    'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 
    'x', 'y', 'z', '{', '|', '}', '~', del);
    -- VHDL'93 includes all 256 ASCII characters

  type severity_level is (note, warning, error, failure); 
  type integer is range -2147483647 to 2147483647; 
  type real is range -1.0E308 to 1.0E308; 
  type time is range -2147483647 to 2147483647 
    units 
      fs;
      ps = 1000 fs;
      ns = 1000 ps;
      us = 1000 ns; 
      ms = 1000 us; 
      sec = 1000 ms; 
      min = 60 sec; 
      hr = 60 min; 
    end units; 
  subtype delay_length is time range 0 fs to time'high;
  impure function now return delay_length; 
  function now return time;    -- VHDL'87 only
  subtype natural is integer range 0 to integer'high; 
  subtype positive is integer range 1 to integer'high; 
  type string is array (positive range <>) of character; 
  type bit_vector is array (natural range <>) of bit; 
  type file_open_kind is (
    read_mode,
    write_mode,
    append_mode);
  type file_open_status is (
    open_ok,
    status_error,
    name_error,
    mode_error);
  attribute foreign: string;
end standard;

注释（Notes）

用户不允许修改标准包的内容。
The user is not allowed to modify the contents of the Standard
package.

TEXTIO包（TEXTIO Package）

Textio包中的的类型和子程序，用来支持操作文本文件的标准化I/O。
Package Textio contains declarations of types and subprograms that support formatted I/O operations on text files.

说明（Description）

Textio允许读取和吸入ASCII文本文件。是LRM的一部分，在库Std中。
Textio is a VHDL package that allows the reading and writing of ASCII text files from VHDL. Textio is part of the LRM, and is in the library Std.

package TEXTIO is
  type LINE is access string;
  type TEXT is file of string;
  type SIDE is (right, left);
  subtype WIDTH is natural;

  file input : TEXT open READ_MODE is "STD_INPUT";
  file output : TEXT open WRITE_MODE is "STD_OUTPUT";

  procedure READLINE(file F: TEXT; L: out LINE);

  procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN);
  procedure READ(L:inout LINE; VALUE: out bit);

  procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN);
  procedure READ(L:inout LINE; VALUE: out bit_vector);

  procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN);
  procedure READ(L:inout LINE; VALUE: out BOOLEAN);

  procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN);
  procedure READ(L:inout LINE; VALUE: out character);

  procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN);
  procedure READ(L:inout LINE; VALUE: out integer);

  procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN);
  procedure READ(L:inout LINE; VALUE: out real);

  procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN);
  procedure READ(L:inout LINE; VALUE: out string);

  procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN);
  procedure READ(L:inout LINE; VALUE: out time);

  procedure WRITELINE(file F : TEXT; L : inout LINE);

  procedure WRITE(L :inout LINE; VALUE : in bit;
                  JUSTIFIED: in SIDE := right;
                  FIELD: in WIDTH := 0);

  procedure WRITE(L : inout LINE; VALUE : in bit_vector;
                  JUSTIFIED: in SIDE := right;
                  FIELD: in WIDTH := 0);

  procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
                  JUSTIFIED: in SIDE := right;
                  FIELD: in WIDTH := 0);

  procedure WRITE(L : inout LINE; VALUE : in character;
                  JUSTIFIED: in SIDE := right;
                  FIELD: in WIDTH := 0);

  procedure WRITE(L : inout LINE; VALUE : in integer;
                  JUSTIFIED: in SIDE := right;
                  FIELD: in WIDTH := 0);

  procedure WRITE(L : inout LINE; VALUE : in real;
                  JUSTIFIED: in SIDE := right;
                  FIELD: in WIDTH := 0;
                  DIGITS: in NATURAL := 0);

  procedure WRITE(L : inout LINE; VALUE : in string;
                  JUSTIFIED: in SIDE := right;
                  FIELD: in WIDTH := 0);

  procedure WRITE(L : inout LINE; VALUE : in time;
                  JUSTIFIED: in SIDE := right;
                  FIELD: in WIDTH := 0;
                  UNIT: in TIME := ns);
end TEXTIO;

注释（Notes）

使用Textio包，要使用library和use语句。
In order to use any of the declarations of the Textio package, the
library and use clauses have to be used.

Std_logic_1164 Package

std_logic_1164定义在库IEEE中。不是VHDL LRM的一部分。
Package std_logic_1164 is defnied in the library IEEE. This package is not part of the VHDL LRM.

说明（Description）

包std_logic_1164用来描述数字逻辑值。包含std_logic（单位）和std_logic_vector（数组）的定义。同时也包含许多VHDL函数，如解决三态冲突的函数，逻辑运算符，转换函数。
The Std_logic_1164 package is the IEEE standard for describing digital logic values in VHDL (IEEE STD 1164). It contains definitions for std_logic (single bit) and for std_logic_vector (array). It also contains VHDL functions for these types to resolve tri-state conflics, functions to define logical operators and conversion functions to and from other standard types.

package std_logic_1164 is
  type std_ulogic is ('u',  -- uninitialized
                      'x',  -- forcing  unknown
                      '0',  -- forcing  0
                      '1',  -- forcing  1
                      'z',  -- high impedance   
                      'w',  -- weak unknown
                      'l',  -- weak 0   
                      'h',  -- weak 1   
                      '-'   -- don't care
  );
  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;

  function resolved ( s : std_ulogic_vector ) return std_ulogic;
  subtype std_logic is resolved std_ulogic;
  type std_logic_vector is array ( natural range <> ) of std_logic;

  subtype x01     is resolved std_ulogic range 'x' to '1'; -- ('x','0','1') 
  subtype x01z    is resolved std_ulogic range 'x' to 'z'; -- ('x','0','1','z') 
  subtype ux01    is resolved std_ulogic range 'u' to '1'; -- ('u','x','0','1') 
  subtype ux01z   is resolved std_ulogic range 'u' to 'z'; -- ('u','x','0','1','z') 

  function "and"  ( l : std_ulogic; r : std_ulogic ) return ux01;
  function "nand" ( l : std_ulogic; r : std_ulogic ) return ux01;
  function "or"   ( l : std_ulogic; r : std_ulogic ) return ux01;
  function "nor"  ( l : std_ulogic; r : std_ulogic ) return ux01;
  function "xor"  ( l : std_ulogic; r : std_ulogic ) return ux01;
  function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01;
  function "not"  ( l : std_ulogic                 ) return ux01;

  function "and"  ( l, r : std_logic_vector  ) return std_logic_vector;
  function "and"  ( l, r : std_ulogic_vector ) return std_ulogic_vector;

  function "nand" ( l, r : std_logic_vector  ) return std_logic_vector;
  function "nand" ( l, r : std_ulogic_vector ) return std_ulogic_vector;

  function "or"   ( l, r : std_logic_vector  ) return std_logic_vector;
  function "or"   ( l, r : std_ulogic_vector ) return std_ulogic_vector;

  function "nor"  ( l, r : std_logic_vector  ) return std_logic_vector;
  function "nor"  ( l, r : std_ulogic_vector ) return std_ulogic_vector;

  function "xor"  ( l, r : std_logic_vector  ) return std_logic_vector;
  function "xor"  ( l, r : std_ulogic_vector ) return std_ulogic_vector;

  function "xnor" ( l, r : std_logic_vector  ) return std_logic_vector;
  function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;

  function "not"  ( l : std_logic_vector  ) return std_logic_vector;
  function "not"  ( l : std_ulogic_vector ) return std_ulogic_vector;

  function to_bit       ( s : std_ulogic;        xmap : bit := '0') return bit;
  function to_bitvector ( s : std_logic_vector ; xmap : bit := '0') return bit_vector;
  function to_bitvector ( s : std_ulogic_vector; xmap : bit := '0') return bit_vector;

  function to_stdulogic       ( b : bit               ) return std_ulogic;
  function to_stdlogicvector  ( b : bit_vector        ) return std_logic_vector;
  function to_stdlogicvector  ( s : std_ulogic_vector ) return std_logic_vector;
  function to_stdulogicvector ( b : bit_vector        ) return std_ulogic_vector;
  function to_stdulogicvector ( s : std_logic_vector  ) return std_ulogic_vector;

  function to_x01  ( s : std_logic_vector  ) return  std_logic_vector;
  function to_x01  ( s : std_ulogic_vector ) return  std_ulogic_vector;
  function to_x01  ( s : std_ulogic        ) return  x01;
  function to_x01  ( b : bit_vector        ) return  std_logic_vector;
  function to_x01  ( b : bit_vector        ) return  std_ulogic_vector;
  function to_x01  ( b : bit               ) return  x01;       

  function to_x01z ( s : std_logic_vector  ) return  std_logic_vector;
  function to_x01z ( s : std_ulogic_vector ) return  std_ulogic_vector;
  function to_x01z ( s : std_ulogic        ) return  x01z;
  function to_x01z ( b : bit_vector        ) return  std_logic_vector;
  function to_x01z ( b : bit_vector        ) return  std_ulogic_vector;
  function to_x01z ( b : bit               ) return  x01z;      

  function to_ux01  ( s : std_logic_vector  ) return  std_logic_vector;
  function to_ux01  ( s : std_ulogic_vector ) return  std_ulogic_vector;
  function to_ux01  ( s : std_ulogic        ) return  ux01;
  function to_ux01  ( b : bit_vector        ) return  std_logic_vector;
  function to_ux01  ( b : bit_vector        ) return  std_ulogic_vector;
  function to_ux01  ( b : bit               ) return  ux01;       

  function rising_edge  (signal s : std_ulogic) return boolean;
  function falling_edge (signal s : std_ulogic) return boolean;

  function is_x ( s : std_ulogic_vector ) return  boolean;
  function is_x ( s : std_logic_vector  ) return  boolean;
  function is_x ( s : std_ulogic        ) return  boolean;
end std_logic_1164;

Numeric_Std Package

The package numeric_std is defnied in the library IEEE. This package is not part of the VHDL LRM.

说明（Description）

IEEE Standard 1076.3 (the numeric standard) was developed to help synthesis tool users and vendors by providing standard, portable data types and operations for numeric data, and by providing more clearly defined meaning for the nine values of the IEEE 1164 std_logic and std_ulogic data types. It defines the package numeric_std.

Two new numeric data types are declared in the numeric_std package:

type unsigned is array (natural range <>) of std_logic;
type signed is array (natural range <>) of std_logic;

Unsigned represents unsigned integer data, signed represents signed integer data in two’s complement form. In signed and unsigned arrays, the leftmost bit is treated as the most significant bit.

Corresponding arithmetic operations and functions are defined in the package for the two data types.