【原语】LUT6-2查找表的应用之加法器

LUT6-2查找表的应用之加法器

通过8个LUT6-2、2个CARRY4级联、9个D触发器做一个加法器（本实验总共实现了7种功能）

LUT6-2框图如下：

CARRY4框图如下：

LUT6-2和CARRY4详细功能请参照Xilinx数据手册

---

Top Module：

`timescale 1ns / 1ps
//
/*	sel[2:0]   function
	3'd0		a+b
	3'd1		a&b
	3'd2		a|b
	3'd3		a+1
	3'd4		b+1
	3'd5		a
	3'd6		b
	3'd7		a+b
*/
module test1(
	input rst,
	input clk,
	input CE,
	input [7:0]a,
	input [7:0]b,
	input [2:0]sel,
	output [8:0]o_sum,
	output [7:0]co
);

	wire [7:0]w_sum;
	wire [7:0]lut_o6;
	wire [7:0]lut_o5;
	
//加1操作只用最低位进行加1，其他位不变，故最低位的LUT初值和其他几位的初值应该不同	
	LUT6_2#(.INIT(64'h800AC0086AC53E86))LUT6_2_inst0(.O6(lut_o6[0]),.O5(lut_o5[0]),.I0(b[0]),.I1(a[0]),.I2(sel[0]),.I3(sel[1]),.I4(sel[2]),.I5(1'b1));
	LUT6_2#(.INIT(64'h800000086ACACE86))LUT6_2_inst1(.O6(lut_o6[1]),.O5(lut_o5[1]),.I0(b[1]),.I1(a[1]),.I2(sel[0]),.I3(sel[1]),.I4(sel[2]),.I5(1'b1));
	LUT6_2#(.INIT(64'h800000086ACACE86))LUT6_2_inst2(.O6(lut_o6[2]),.O5(lut_o5[2]),.I0(b[2]),.I1(a[2]),.I2(sel[0]),.I3(sel[1]),.I4(sel[2]),.I5(1'b1));
	LUT6_2#(.INIT(64'h800000086ACACE86))LUT6_2_inst3(.O6(lut_o6[3]),.O5(lut_o5[3]),.I0(b[3]),.I1(a[3]),.I2(sel[0]),.I3(sel[1]),.I4(sel[2]),.I5(1'b1));
	LUT6_2#(.INIT(64'h800000086ACACE86))LUT6_2_inst4(.O6(lut_o6[4]),.O5(lut_o5[4]),.I0(b[4]),.I1(a[4]),.I2(sel[0]),.I3(sel[1]),.I4(sel[2]),.I5(1'b1));
	LUT6_2#(.INIT(64'h800000086ACACE86))LUT6_2_inst5(.O6(lut_o6[5]),.O5(lut_o5[5]),.I0(b[5]),.I1(a[5]),.I2(sel[0]),.I3(sel[1]),.I4(sel[2]),.I5(1'b1));
	LUT6_2#(.INIT(64'h800000086ACACE86))LUT6_2_inst6(.O6(lut_o6[6]),.O5(lut_o5[6]),.I0(b[6]),.I1(a[6]),.I2(sel[0]),.I3(sel[1]),.I4(sel[2]),.I5(1'b1));
	LUT6_2#(.INIT(64'h800000086ACACE86))LUT6_2_inst7(.O6(lut_o6[7]),.O5(lut_o5[7]),.I0(b[7]),.I1(a[7]),.I2(sel[0]),.I3(sel[1]),.I4(sel[2]),.I5(1'b1));
	
	CARRY4 CARRY4_inst0(.CO(co[3:0]),.O(w_sum[3:0]),.CI(1'b0),.CYINIT(1'b0),.DI(lut_o6[3:0]),.S(lut_o5[3:0]));
	CARRY4 CARRY4_inst1(.CO(co[7:4]),.O(w_sum[7:4]),.CI(co[3]),.CYINIT(1'b0),.DI(lut_o6[7:4]),.S(lut_o5[7:4]));
	
	FDRE FDRE_inst0(.Q(o_sum[0]),.C(clk),.CE(CE),.R(rst),.D(w_sum[0]));
	FDRE FDRE_inst1(.Q(o_sum[1]),.C(clk),.CE(CE),.R(rst),.D(w_sum[1]));
	FDRE FDRE_inst2(.Q(o_sum[2]),.C(clk),.CE(CE),.R(rst),.D(w_sum[2]));
	FDRE FDRE_inst3(.Q(o_sum[3]),.C(clk),.CE(CE),.R(rst),.D(w_sum[3]));
	FDRE FDRE_inst4(.Q(o_sum[4]),.C(clk),.CE(CE),.R(rst),.D(w_sum[4]));
	FDRE FDRE_inst5(.Q(o_sum[5]),.C(clk),.CE(CE),.R(rst),.D(w_sum[5]));
	FDRE FDRE_inst6(.Q(o_sum[6]),.C(clk),.CE(CE),.R(rst),.D(w_sum[6]));
	FDRE FDRE_inst7(.Q(o_sum[7]),.C(clk),.CE(CE),.R(rst),.D(w_sum[7]));
	FDRE FDRE_inst8(.Q(o_sum[8]),.C(clk),.CE(CE),.R(rst),.D(co[7]));
	
endmodule

TestBench:

`timescale 1ns / 1ps
`define clk_period 20
module test1_tb;

	// Inputs
	reg rst;
	reg clk;
	reg CE;
	reg [7:0] a;
	reg [7:0] b;
	reg [2:0]sel;
	// Outputs
	wire [8:0] o_sum;
	wire [7:0] co;

	// Instantiate the Unit Under Test (UUT)
	test1 uut (
		.rst(rst), 
		.clk(clk), 
		.CE(CE), 
		.a(a), 
		.b(b), 
		.o_sum(o_sum), 
		.co(co),
		.sel(sel)
	);

	initial clk= 1;
	always#(`clk_period/2) clk = ~clk;
	
	initial begin
		// Initialize Inputs
		rst = 1;
		clk = 0;
		CE = 0;
		a = 0;
		b = 0;
		sel = 0;
		// Wait 100 ns for global reset to finish
		#100;
		rst = 0;
		CE = 1;
      	a = 8'd3;
		b = 8'd4;
		sel = 3'd0;
		#20;
		sel = 3'd1;
		#20;
		sel = 3'd2;
		#20;
		sel = 3'd3;
		#20;
		sel = 3'd4;
		#20;
		sel = 3'd5;
		#20;
		sel = 3'd6;
		#20;
		sel = 3'd7;
		#20;
        a = 8'd15;
		b = 8'd21;
		sel = 3'd3;
		#20;
		a = 8'd13;
		b = 8'd26;
		sel = 3'd4;
		#20;
		// Add stimulus here
	end
endmodule

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LUT6-2的真值表