“11010“ 序列检测器

用有限状态机做，状态机的题主要是用模板做，三段式或者两段式，要画出正确的状态转移图

见Verilog p109

module seqdet(D_out,D_in,rst_n,clk);
    parameter IDLE = 3'd0,A = 3'd1,B = 3'd2,C = 3'd3,D = 3'd4,E = 3'd5;
    output D_out;
    input D_in,rst_n,clk;
    reg [2:0] state,next_state;
    wire D_out;

    assign D_out = (state == E)?1:0; 

    always@(state or D_in)
        case(state)
            IDLE:if(D_in) next_state = A;
                 else next_state = IDLE;
            A:if(D_in) next_state = B;
                else next_state = IDLE;
            B:if(D_in) next_state = B;
                else next_state = C;
            C:if(D_in) next_state = D;
                else next_state = IDLE;
            D:if(D_in) next_state = B;
                else next_state = E;
            E:if(D_in) next_state = IDLE;
                else next_state = A;
            default: next_state = IDLE;
        endcase

        always@(posedge clk)
            state <= next_state;

endmodule