Vivado编译报错解决合集

报错问题1：

23.06.23：

        在implementation时报错：[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I2, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/refresh_generation.refresh_bank_r[0]_i_1.
解决方法：

           检查接口，mig IP核调用的时候有空接口，保留接口也要接1‘b0

报错问题2：

2022.06.27：

implementation 时报错：[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_clk_wiz_0/inst/clk_in1_clk_wiz_0] >

    u_clk_wiz_0/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y74
     u_clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2

    The above error could possibly be related to other connected instances. Following is a list of 
    all the related clock rules and their respective instances.

    Clock Rule: rule_mmcm_bufg
    Status: PASS 
    Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
     u_clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
     and u_clk_wiz_0/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

解决方法：

        XDC文件时序约束有问题，应该是调用PLL时钟的问题，在XDC文件中加入以下时序约束：

< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_clk_wiz_0/inst/clk_in1_clk_wiz_0] >

即可，虽然最后也没用上。