VHDL

最新推荐文章于 2024-08-10 21:29:54 发布

Sherduo

最新推荐文章于 2024-08-10 21:29:54 发布

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分类专栏： EDA 文章标签： VHDL

本文链接：https://blog.csdn.net/Sherduo/article/details/52976217

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3 篇文章 1 订阅

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一. 四位加法计数器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt4b is 
    port (
            clk  : in std_logic;
            rst  : in std_logic;
            ena  : in std_logic;
            outy : out std_logic_vector(3 downto 0);
            cout : out std_logic
          );
    end entity cnt4b;

architecture behav of cnt4b is
    signal cqi :std_logic_vector(3 downto 0);
begin 
    process(clk,rst,ena)
    begin
      if    rst ='1' then  cqi <="0000";
      elsif clk'event and clk ='1' then
        if  ena='1' then cqi <= cqi+1;
        end if;
      end if;
        outy <=cqi;
    end process;
    cout <=cqi(0) and cqi(1) and cqi(2) and cqi(3);
end architecture behav;

二. 七段译码器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 ENTITY DecL7s IS
   PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END ENTITY DecL7s;
ARCHITECTURE one OF DecL7S IS
BEGIN
   PROCESS(A)
   BEGIN
       CASE A(3 DOWNTO 0) IS
        WHEN "0000" => LED7S <= "0111111";
        WHEN "0001" => LED7S <= "0000110";
        WHEN "0010" => LED7S <= "1011011";
        WHEN "0011" => LED7S <= "1001111";
        WHEN "0100" => LED7S <= "1100110";
        WHEN "0101" => LED7S <= "1101101";
        WHEN "0110" => LED7S <= "1111101";
        WHEN "0111" => LED7S <= "0000111";
        WHEN "1000" => LED7S <= "1111111";
        WHEN "1001" => LED7S <= "1101111";
        WHEN "1010" => LED7S <= "1110111";
        WHEN "1011" => LED7S <= "1111100";
        WHEN "1100" => LED7S <= "0111001";
        WHEN "1101" => LED7S <= "1011110";
        WHEN "1110" => LED7S <= "1111001";
        WHEN "1111" => LED7S <= "1110001";
        WHEN OTHERS => NULL;
       END CASE;
   END PROCESS;
END ARCHITECTURE one;

三. 寄存器

LIBRARY IEEE;   
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY REG4B IS 
    PORT (   
            LK   : IN STD_LOGIC; 
            DIN  : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
            DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) 
         ); 
END REG4B; 

ARCHITECTURE behav OF REG4B IS 
BEGIN 
    PROCESS(LK, DIN) 
    BEGIN 
      IF LK'EVENT AND LK = '1' THEN  DOUT <= DIN; 
      END IF; 
    END PROCESS; 
END behav;

四. 频率计测控器（分频器待改进）

LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY FTCTRL IS 
    PORT (
            CLKK : IN STD_LOGIC;                  
          CNT_EN : OUT STD_LOGIC;                 
         RST_CNT : OUT STD_LOGIC;               
            Load : OUT STD_LOGIC   
          );              
END FTCTRL; 

ARCHITECTURE behav OF FTCTRL IS 
    SIGNAL Div2CLK : STD_LOGIC; 
BEGIN 
    PROCESS( CLKK ) 
    BEGIN 
      IF CLKK'EVENT AND CLKK = '1' THEN      
        Div2CLK <= NOT Div2CLK; 
      END IF; 
    END PROCESS; 

    PROCESS (CLKK, Div2CLK) 
    BEGIN 
      IF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1';
      ELSE RST_CNT <= '0';  END IF; 
    END PROCESS; 
    Load  <= NOT Div2CLK;    CNT_EN <= Div2CLK; 
END behav;

五. 状态机

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY SCHK IS
  PORT(DIN,CLK,CLR : IN STD_LOGIC;
       AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END SCHK;
ARCHITECTURE BEHAV OF SCHK IS 
  SIGNAL Q : INTEGER RANGE 0 TO 8;
  SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0); 
BEGIN
  D<="11110000"; 
  PROCESS(CLK,CLR) 
  BEGIN
IF CLR = '1' THEN Q<=0;
ELSIF CLK'EVENT AND CLK='1' THEN 
  CASE Q IS
  WHEN 0=> IF DIN=D(7) THEN Q<=1; ELSE Q<=0; END IF; 
  WHEN 1=> IF DIN=D(6) THEN Q<=2; ELSE Q<=0; END IF; 
  WHEN 2=> IF DIN=D(5) THEN Q<=3; ELSE Q<=0; END IF; 
  WHEN 3=> IF DIN=D(4) THEN Q<=4; ELSE Q<=0; END IF; 
  WHEN 4=> IF DIN=D(3) THEN Q<=5; ELSE Q<=0; END IF; 
  WHEN 5=> IF DIN=D(2) THEN Q<=6; ELSE Q<=0; END IF; 
  WHEN 6=> IF DIN=D(1) THEN Q<=7; ELSE Q<=0; END IF; 
  WHEN 7=> IF DIN=D(0) THEN Q<=8; ELSE Q<=0; END IF; 
  END CASE; 
END IF;
END PROCESS; 
PROCESS(Q) 
BEGIN
  IF Q=8 THEN AB<="1111"; 
  ELSE AB<="0101";
  END IF; 
END PROCESS;
END BEHAV;

状态机序列检测器（改进版）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY aaa IS
    PORT(
       CLK,CLR : IN STD_LOGIC;
           DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
        );
END aaa;

ARCHITECTURE BEHAV OF aaa IS 
    SIGNAL Q : INTEGER RANGE 0 TO 8;
    SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0); 
BEGIN
    D<="10110001"; 
    PROCESS(CLK,CLR) 
    BEGIN
      IF CLR = '1' THEN Q<=0;
      ELSIF CLK'EVENT AND CLK='1' THEN 
        IF    DIN(7)=D(7) AND DIN(6)=D(6) 
          AND DIN(5)=D(5) AND DIN(4)=D(4) 
          AND DIN(3)=D(3) AND DIN(2)=D(2) 
          AND DIN(1)=D(1) AND DIN(0)=D(0) THEN Q<=8; ELSE Q<=0; END IF;
      END IF;
    END PROCESS; 

    PROCESS(Q) 
      BEGIN
        CASE Q IS
          WHEN      8 => AB<="1111"; 
          WHEN OTHERS => AB<="0000";
       END CASE;
END PROCESS;
END BEHAV;

六. 数据选择器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX IS
    PORT(
            CLK,S0,S1 : IN STD_LOGIC;
                A,B,C : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    Y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
END MUX;

ARCHITECTURE BEHAV OF MUX IS 
    SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
    S <= S1&S0;
    PROCESS(S)
    BEGIN
      IF CLK'EVENT AND CLK = '1' THEN
        CASE S IS 
          WHEN "00" => Y <= A;
          WHEN "01" => Y <= B;
          WHEN "10" => Y <= C;
        --WHEN "11" => Y <= D;
          WHEN OTHERS => NULL;
        END CASE;
      END IF;
    END PROCESS;
END BEHAV;

七. 各种波形
正弦波

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SINGT IS
    PORT(
            CLK  : IN STD_LOGIC;         
            DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
END ENTITY;

ARCHITECTURE DACC OF SINGT IS
COMPONENT SIN_ROM    
    PORT(
            address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
              clock : IN STD_LOGIC ;
                  q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
END COMPONENT;

    SIGNAL Q1 : STD_LOGIC_VECTOR (5 DOWNTO 0); 
    BEGIN
    PROCESS(CLK)                           
      BEGIN
        IF CLK'EVENT AND CLK = '1' THEN  Q1 <= Q1+1;
        END IF;
    END PROCESS;

U1 : SIN_ROM PORT MAP(address => Q1, q => DOUT,clock => CLK);

END DACC;

方波（算法有待改进）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SQUARE IS
    --GENERIC (D : INTEGER := 4);
    PORT(
            CLK : IN STD_LOGIC;
            DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
            CIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
              Q : OUT INTEGER RANGE 0 TO 250
        );
END SQUARE;

ARCHITECTURE BEHAV OF SQUARE IS
    SIGNAL     D : INTEGER;
    SIGNAL COUNT : INTEGER;

BEGIN
  PROCESS(DIN,CLK)
  BEGIN
    IF CLK'EVENT AND CLK = '1' THEN
      CASE(DIN) IS
        WHEN "00" =>  D <= 2;
        WHEN "01" =>  D <= 3;
        WHEN "10" =>  D <= 4;
        WHEN "11" =>  D <= 5;
      END CASE;
    END IF;
  END PROCESS;

  PROCESS(DIN,CLK)
  BEGIN
    IF CLK'EVENT AND CLK = '1' THEN
      CASE(CIN) IS
        WHEN "00" =>  COUNT <= 3;
        WHEN "01" =>  COUNT <= 2;
        WHEN "10" =>  COUNT <= 1;
        WHEN "11" =>  COUNT <= 0;
      END CASE;
    END IF;
  END PROCESS;

  PROCESS(CLK,D,COUNT)
    VARIABLE COUNT : INTEGER := 0;
    BEGIN
      IF CLK'EVENT AND CLK = '1' THEN
        IF COUNT >= D-1 THEN
          COUNT := 0;
          Q <= 0;
        ELSE
          COUNT := COUNT+1;
          Q <= 250;
        END IF;
      END IF;
    END PROCESS;
END BEHAV;

锯齿波

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JUCHI IS
    PORT(
            CLK  : IN STD_LOGIC;         
            DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
END ENTITY;

ARCHITECTURE DAC OF JUCHI IS
COMPONENT JUCHI_ROM    
    PORT(
            address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
              clock : IN STD_LOGIC ;
                  q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
END COMPONENT;

    SIGNAL Q1 : STD_LOGIC_VECTOR (5 DOWNTO 0); 
    BEGIN
    PROCESS(CLK)                           
      BEGIN
        IF CLK'EVENT AND CLK = '1' THEN  Q1 <= Q1+1;
        END IF;
    END PROCESS;

J1 : JUCHI_ROM PORT MAP(address => Q1, q => DOUT,clock => CLK);

END DAC;