Verilog

一. 门级结构描述

D触发器

module dflop(q,qb,clear,data,clk); 
    input clear,data,clk; 
    output q,qb; 
        not U5(net4,data);
        nand U1(net1,clear,data,clk);
        nand U6(net5,net4,clk);    
        nand U2(net2,net1,net6);
        nand U7(net6,clear,net5,net2);     
        not U10(net8,clk);     
        nand U3(net3,net2,net8);
        nand U8(net7,net6,net8); 
        nand U4(q,net3,qb);
        nand U9(qb,net7,clear,q);     
endmodule

四位移位寄存器

module SHIFT_REGI(q,qb,clear,data,clk); 
    input data, clear, clk;               
    output [3:0]q, qb;                                                
    dflop f3(q[3],qb[3],clear,data,clk),                 
          f2(q[2],qb[2],clear,q[3],clk),              
          f1(q[1],qb[1],clear,q[2],clk),        
          f0(q[0],qb[0],clear,q[1],clk);
 endmodule 

四位移位寄存器测试文件

`timescale 10ns/10ns
 module SHIFT_REGI_testbench;  
    reg clk,clear,data;   
    wire [3:0] q,qb;   
initial   
    begin    
      clk = 0;     
      clear = 0;     
      data=0;     
      #40  clear = 1;     
      #200 clear = 0;     
      #100 $stop;   
    end   
always #5 clk = ~clk;   
always @(posedge clk)   
    data={$random}%2;   
SHIFT_REGI m1(q,qb,clear,data,clk);   
endmodule

二. 行为描述
四位计数器

module counter_4bits(Q,CLR,CLK);
    input CLR,CLK;
    output reg[3:0]Q;
    always@(negedge CLK)
      begin
        if(CLR) 
          Q<=4'b0000;
        else
          Q<=Q+4'b0001;
      end
endmodule

测试文件

`timescale 10ns/10ns
module counter_4Bits_testbench;
    reg CLR,CLK;
    wire [3:0] Q;
initial
    $monitor($time, "Count Q = %b Clear=%b",Q[3:0],CLR); 
initial
    begin
      CLK = 1'b0;
      forever #5 CLK=~CLK; 
    end
initial
    begin
      CLR = 1'b1;
      #10  CLR = 1'b0; 
      #200 CLR = 1'b1; 
      #30  $stop;
    end
counter_4bits C1(Q,CLR,CLK);
endmodule

模十计数器（模）

module couter_mo10(Q