基于FPGA的60进制实验

基于FPGA的60进制实验
0、电路图

1、分频

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_ARITH.all;

--//=======================================
entity clkdiv is
port(clk50M:IN STD_LOGIC;--时钟20MHZ
	 clk1KHZ,clk1HZ:buffer STD_LOGIC);
END clkdiv;
--//=======================================
architecture behave of clkdiv is
begin
--//============分频产生1000HZ=============== 
	process(clk50M)
	variable count1:integer range 24999 downto 0;
	variable temp1:STD_LOGIC;
	BEGIN
		if clk50M 'event and clk50M='1' then
			if count1=24999 then
			temp1:=not temp1;
			count1:=0;
			else
			count1:=count1+1;
			end if;
		end if;
		clk1KHZ<=temp1;
	end process;