FPGA学习笔记9---十进制模60计数器

module sixty(
input clk,
input rst_n,
input load,
output reg [5:0]cnt
);
always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
	cnt<=6'd0;
	else if(load)
	cnt<=6'd30;
	else if(cnt==6'd59)
	cnt<=6'd0;
	else cnt<=cnt+1'b1;
	end

endmodule

module tb_sixty();
reg clk,load,rst_n;
wire [5:0]cnt;
sixty st(.clk(clk),.load(load),.rst_n(rst_n),.cnt(cnt));
initial begin
load<=1'b1;
clk<=1'b0;
rst_n<=1'b0;
#20 rst_n<=1'b1;
#50 load <=1'b0;
end

always # 5 clk<=~clk;

endmodule