前言
一、VGA模块的构建
对于VGA模块的构建,我们分为三个模块,及clk_wiz_0PLL、vga_drive(VGA的驱动模块)、frame_controller(图像帧产生模块)。
具体实现的流程图,可参考如上。本次实验是通过将图片处理成COE文件,再放进ROM中,Frame_Controller模块将rom中的数据读出,送到image_Process模块图像处理进行处理,将处理完的数据,送到Vga_Driver驱动输出。
1.VGA_drive
module vga_drive:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2021/12/27 11:33:17
// Design Name:
// Module Name: vga_drive
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module vga_drive(
input vga_clk,
input wire rst_n,
input wire [15:0] rgb_data,//rgb565
output wire [11:0] vga_data,//rgb444
output wire vga_hsync,
output wire vga_vsync,
output wire [9:0] pos_x,
output wire [9:0] pos_y,
output vga_data_vaild
);
//分辨率 640 *480
parameter H_SYNC = 10'd96,
H_BACK = 10'd40,
H_LEFT = 10'd8,
H_VALID = 10'd640,
H_RIGHT = 10'd8,
H_FRONT = 10'd8,
H_TOTAL = 10'd800;
parameter V_SYNC = 10'd2,
V_BACK = 10'd25,
V_LEFT = 10'd8,
V_VALID = 10'd480,
V_RIGHT = 10'd8,
V_FRONT = 10'd2,
V_TOTAL = 10'd525;
//---------------------------------------------
reg [9:0]h_cnt;
reg [9:0]v_cnt;
//wire vga_data_vaild;
//wire [9:0] pos_x;
//wire [9:0] pos_y;
//--------------------------------------------------------------
//---------------------------------核心代码---------------------
//---------------------------------------------------------------
//-----------------行扫描------------------------
always@(posedge vga_clk or negedge rst_n)
if(!rst_n)
begin
h_cnt <= 10