VCS编译时可以添加的option:
kdb
: ? dump verdi?
vcs - assert dve
:
把assertion放入vpd文件中,并支持在dve中的trace
-R
编译以后立即自动执行,原来的runtime参数也应该带上(即不必再用simv)来执行了
-cm line+cond+fsm+tgl+branch+assert
:
可以收集由以下信息带来的的coverage:
- line:Line or statement coverage
- cond: condition coverage
- fsm
- tgl
- branch: branch coverage
- assert: Enable collecting SystemVerilog assertion coverage