-
FPGA代码模板
代码模板0：
module ad9253_driver #(
parameter BIT_REVERSE = 1
)(
input sys_clk ,//(i)
input sys_rst_n ,//(i)
input clk_200m ,//(i)
input sync_in ,//(i)
output adc_0_data_clk ,//(o)
output [15:0] adc_0_a_data ,//(o)
output [15:0] adc_0_b_data ,//(o)
output [15:0] adc_0_c_data ,//(o)
output [15:0] adc_0_d_data ,//(o)
output ADC_0_SPI_CSB ,//(o)
output ADC_0_SYNC ,//(o)
output ADC_0_PDWN //(o)
);
// -------------------------------------------------------------------------
// Internal Parameter Definition
// -------------------------------------------------------------------------
//localparam IDLE = 4'h00 ;
//---------------------------------------------------------------------
// Defination of Internal Signals
//---------------------------------------------------------------------
//reg [3:0] sta ;
// -------------------------------------------------------------------------
// output
// -------------------------------------------------------------------------
//assign program_b = sta == PROG ;
// =================================================================================================
// RTL Body
// =================================================================================================
// always@(posedge sys_clk or negedge sys_rst_n) begin
// if(~sys_rst_n)begin
// cfg_rst_d1 <= 1'd0;
// cfg_rst_d2 <= 1'd0;
// end else begin
// cfg_rst_d1 <= cfg_rst;
// cfg_rst_d2 <= cfg_rst_d1;
// end
// end
// -------------------------------------------------------------------------
// cmip_edge_sync Module Inst.
// -------------------------------------------------------------------------
endmodule代码模板1：
// =================================================================================================
// Copyright 2020 - 2030 (c) Semi, Inc. All rights reserved.
// =================================================================================================
//
// =================================================================================================
// File Name : name.v
// Module : name
// Function :
// Type : RTL
// -------------------------------------------------------------------------------------------------
// Update History :
// -------------------------------------------------------------------------------------------------
// Rev.Level Date Coded by Contents
// 0.1.0 2023/01/05 Holt Create new
//
// =================================================================================================
// End Revision
// =================================================================================================
module name #(
parameter OUTBITW = 8 ,
parameter INBITW = 16 ,
parameter BUS_DELAY = 1
)(
input clk ,//(i)
input rst_n ,//(i)
input i_vld ,//(i)
input [INBITW -1:0] i_data ,//(i)
output o_vld ,//(o)
output [OUTBITW -1:0] o_data //(o)
);
// -------------------------------------------------------------------------
// Internal Parameter Definition
// -------------------------------------------------------------------------
//---------------------------------------------------------------------
// Defination of Internal Signals
//---------------------------------------------------------------------
(* KEEP = "TRUE", MARK_DEBUG = "TRUE" *)wire [OUTBITW -1:0] data_res ;
wire pip_vld ;
wire [OUTBITW -1:0] pip_data ;
// -------------------------------------------------------------------------
// output
// -------------------------------------------------------------------------
assign data_res = i_data[INBITW-1:INBITW-OUTBITW];
assign o_vld = pip_vld ;
assign o_data = pip_data ;
// =================================================================================================
// RTL Body
// =================================================================================================
//---------------------------------------------------------------------
// pipeline
//---------------------------------------------------------------------
generate if(BUS_DELAY==0) begin
assign pip_vld = i_vld ;
assign pip_data = data_res ;
end else begin
cmip_bus_delay #(
.BUS_DELAY (BUS_DELAY ),
.DATA_WDTH (OUTBITW + 1 )
)u_cmip_bus_delay(
.i_clk (clk ),//(i)
.i_rst_n (rst_n ),//(i)
.i_din ({i_vld , data_res }),//(i)
.o_dout ({pip_vld , pip_data }) //(o)
);
end
endgenerate
endmodule
代码模板2：
module name #(
parameter SIN_DATA_WD = 11 ,
parameter POS_DATA_WD = 18
)(
input clk ,//(i)
input rst_n ,//(i)
input sin_vld ,//(i)
input [SIN_DATA_WD -1:0] sin_data ,//(i)
output [POS_DATA_WD -1:0] notch_pos ,//(o)
output [SIN_DATA_WD -1:0] notch_val ,//(o)
output [SIN_DATA_WD -1:0] max_val ,//(o)
output [SIN_DATA_WD -1:0] min_val ,//(o)
output [SIN_DATA_WD -1:0] mid_val ,//(o)
output cpl ,//(o)
output [POS_DATA_WD -1:0] pos_cnt //(o)
);
// -------------------------------------------------------------------------
// Internal Parameter Definition
// -------------------------------------------------------------------------
// localparam FIFO_WDTH = EDS_DATA_WD * NUM ;
//---------------------------------------------------------------------
// Defination of Internal Signals
//---------------------------------------------------------------------
// reg [9:0] cnt ;
// -------------------------------------------------------------------------
// output
// -------------------------------------------------------------------------
// assign sop_d0 = &eds_data[BUS_DATA_WD-1:EDS_DATA_WD] & eds_vld ;
// =================================================================================================
// RTL Body
// =================================================================================================
//---------------------------------------------------------------------
// pipeline
//---------------------------------------------------------------------
// always @(posedge clk or negedge rst_n) begin
// if(~rst_n)begin
// for(i=0;i<NUM;i=i+1)
// tap_d1[i] <= {EDS_DATA_WD{1'b0}};
// end else begin
// for(i=0;i<NUM;i=i+1)
// tap_d1[i] <= tap_d0[i];
// end
// end
endmodule
-
FPGA状态机模板
// -------------------------------------------------------------------------
// Internal Parameter Definition
// -------------------------------------------------------------------------
localparam IDLE = 8'h00 ;//
localparam RBD = 8'h01 ;//read buffer descriptor.
localparam WAIT = 8'h02 ;//descriptor need read again.
localparam ERR = 8'h04 ;//descriptor context has err.
localparam CPY = 8'h08 ;//start cdma.
localparam WBD = 8'h10 ;//write buffer descriptor.
localparam STOP = 8'h20 ;//according circle mode,decide whether stop sta.
// -------------------------------------------------------------------------
// FSM logic.
// -------------------------------------------------------------------------
always@(posedge axi_clk or negedge axi_rst_n)
if(!axi_rst_n)begin
sta <= IDLE;
end else begin
case(sta)
IDLE :if(run_trig)
sta <= RBD ;
else
sta <= IDLE;
RBD :if(rbd_cpl && rbd_has_err)
sta <= ERR ;
else if(rbd_cpl && rbd_wait && cfg_wait_mode_en )
sta <= WAIT;
else if(rbd_cpl)
sta <= CPY ;
WAIT :if(wait_ok)
sta <= RBD ;
else
sta <= WAIT;
ERR : sta <= WBD ;
CPY :if(cpy_cpl)
sta <= WBD ;
else
sta <= CPY ;
WBD :if(wbd_cpl)
sta <= STOP;
else
sta <= IDLE;
STOP :if(cfg_cycle_mode_en || (~eof))
sta <= RBD ;
else
sta <= IDLE;
default: sta <= IDLE;
endcase
end-
Vivado常用约束
create_clock -period 5.000 [get_ports clk_200_p]
create_clock -period 6.400 [get_ports gtxq1_p]
set_false_path -from [get_clocks clk_out1_clk_wiz_0] -to [get_clocks rxoutclk_out[0]]
set_false_path -from [get_clocks clk_out1_clk_wiz_0] -to [get_clocks rxoutclk_out[0]_1]
set_false_path -from [get_clocks clk_out1_clk_wiz_0] -to [get_clocks txoutclk_out[0]]
set_false_path -from [get_clocks clk_out1_clk_wiz_0] -to [get_clocks txoutclk_out[0]_1]
set_false_path -from [get_clocks clk_out3_clk_wiz_0] -to [get_clocks txoutclk_out[0]]
set_false_path -from [get_clocks clk_out3_clk_wiz_0] -to [get_clocks txoutclk_out[0]_1]
#set_max_delay -from [get_clocks clk_out1_clk_wiz_0] -to [get_clocks {txoutclk_out[0]}] 10.000
#set_max_delay -from [get_clocks clk_out1_clk_wiz_0] -to [get_clocks {txoutclk_out[0]_1}] 10.000
#----------------------HDMI接口---------------------------
set_property -dict {IOSTANDARD TMDS_33} [get_ports tmds_clk_n]
set_property -dict {IOSTANDARD TMDS_33 PACKAGE_PIN H16} [get_ports tmds_clk_p]
set_property -dict {IOSTANDARD TMDS_33 PACKAGE_PIN D19} [get_ports {tmds_data_p[0]}]
set_property -dict {IOSTANDARD TMDS_33} [get_ports {tmds_data_n[0]}]
set_property -dict {IOSTANDARD TMDS_33 PACKAGE_PIN C20} [get_ports {tmds_data_p[1]}]
set_property -dict {IOSTANDARD TMDS_33} [get_ports {tmds_data_n[1]}]
set_property -dict {IOSTANDARD TMDS_33 PACKAGE_PIN B19} [get_ports {tmds_data_p[2]}]
set_property -dict {IOSTANDARD TMDS_33} [get_ports {tmds_data_n[2]}]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN F17} [get_ports tmds_oen]
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
set_clock_groups -name async_clk_group -asynchronous \
-group [get_clocks -include_generated_clocks {clk_out1_clk_wiz_0}] \
-group [get_clocks -include_generated_clocks {rxoutclk_out[0]}]
# 所有时钟都异步，用于快速制作版本，一般不推荐这么使用
create_clock -period 2.500 -name ADC_1_4_DCO [get_ports ADC_1_4_DCO_P]
create_clock -period 2.500 -name ADC_5_8_DCO [get_ports ADC_5_8_DCO_P]
create_clock -period 2.500 -name ADC_9_12_DCO [get_ports ADC_9_12_DCO_P]
create_clock -period 2.500 -name ADC_13_16_DCO [get_ports ADC_13_16_DCO_P]
create_clock -period 2.500 -name ADC_17_20_DCO [get_ports ADC_17_20_DCO_P]
create_clock -period 2.500 -name ADC_21_24_DCO [get_ports ADC_21_24_DCO_P]
create_clock -period 2.500 -name ADC_25_28_DCO [get_ports ADC_25_28_DCO_P]
create_clock -period 2.500 -name ADC_29_32_DCO [get_ports ADC_29_32_DCO_P]
set_clock_groups -name async_clk_group -asynchronous -group [get_clocks FPGA_MASTER_CLOCK_P -include_generated_clocks] -group [get_clocks ADC_1_4_DCO] -group [get_clocks ADC_5_8_DCO -include_generated_clocks]\
-group [get_clocks ADC_9_12_DCO -include_generated_clocks] -group [get_clocks ADC_13_16_DCO -include_generated_clocks]\
-group [get_clocks ADC_17_20_DCO -include_generated_clocks] -group [get_clocks ADC_21_24_DCO -include_generated_clocks]\
-group [get_clocks ADC_25_28_DCO -include_generated_clocks] -group [get_clocks ADC_29_32_DCO -include_generated_clocks]
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