- MATLAB中生成rom可以读的.coe文件:
clc;
clear all;
close all;
width = 8; %位宽
depth = 2 ^ 8 * 2; %深度(采样点个数)
x = linspace(0, 2 * pi, depth);
y = sin(x);
y = round(y * (2 ^ (width - 1) - 1) + 2 ^ (width - 1) - 1);%量化
plot(y);
fid = fopen('dds_sin.coe','w');
fprintf(fid,'memory_initialization_radix=10;\n');
fprintf(fid,'memory_initialization_vector =\n');
fprintf(fid, '%d,\n', y);
fclose(fid);
其中,.coe文件最终格式如下:
memory_initialization_radix=10;
memory_initialization_vector =
127,
129,
130,
132,
…
127;
(第一行表明数据进制类型,第二部分写数据向量,以,隔开,以;结尾)
数据:位宽8位,深度设置为2 * 2 ^ 8(尽量保证每个量化数据处都有一个点)。
- 配置vivado中rom的ip核
任意打开一个project->
例化ip核的格式:
design:
`timescale 1ps / 1ps
module sin_test(
input clk,
input rst,
output sin_data
);
parameter WD = 8;//bit width
parameter step = 9'd1;
parameter depth = 9'd511;
wire [8:0] sin_data;
reg [WD:0] address;//accumulator as address of rom
always @(posedge clk or negedge rst)
begin
if(!rst) address = 9'd0;
else if(address < depth) address = address + step;
else address = 9'd0;
end
dist_mem_gen_0 rom1 (
.a(address),
.clk(clk),
.spo(sin_data)
);
endmodule
simulation:
`timescale 1ps / 1ps
module sin_sim();
reg clk, rst;
wire [8:0]sin_data;
sin_test sin_1(clk, rst, sin_data);
initial
begin
clk = 1'b0;
rst = 1'b1;
end
always
#5 clk = ~clk;
/*always @(rst)
begin
#5120 rst = 1'b0;
#10 rst = 1'b1;
end*/
endmodule
仿真结果: