Verilog不完整if else,case锁存

1前提

仅在组合逻辑电路(电平触发)中产生锁存, 因时序逻辑电路本身具有存储功能(边沿触发, 边沿到来前保持原状)

2验证

2.1 if…else

module latchOrDff(
clk,
data,
enable,
q );
input clk,data,enable;
output q;
reg q;
always @(posedge clk) begin
    if (enable) 
        q<=data;
    //else 
    //    q=1'b0
end
endmodule

去掉注释后:

module latchOrDff(
//clk,
data,
enable,
q );
input data,enable;
output q;
reg q;
always @(enable or data) begin
    if (enable) 
        q=data;
    //else 
    //    q=1'b0;//若写q=q;仍锁存器
end
endmodule

(↑RTL ANALYSIS Schematic if-else以上三种情况)

去掉注释后:

↑仅此处无reg,因二选一选择器不存值

2.2 case

module latchOrDff(
clk,
data,
enable,
q );
input clk,data,enable;
output q;
reg q;
always @(posedge clk) begin
    case (enable) 
    1'b1: q=data;
    //1'b0: q=1'b0;
    //default: q=1'b0;
end
endmodule

RTL图同if else

module latchOrDff(
//clk,
data,
enable,
q );
input data,enable;
output q;
reg q;
always @(enable or data) begin
    case (enable) 
    1'b1: q=data;
    //1'b0: q=1'b0;
    //default: q=1'b0;//若写q=q;仍锁存器
end
endmodule

3小结

1. 逻辑电路中if 补else, case补default
2. 补的内容不能锁存(赋原值)

4绝佳的参考文章

https://blog.csdn.net/qq_40696831/article/details/88855164