Verilog开发中阻塞“=”和非阻塞“＜=”的区别

module top_module ();
reg clk=0;
reg rstn;
always #5 clk = ~clk; // Create clock with period=10
initial `probe_start; // Start the timing diagram

`probe(clk);        // Probe signal "clk"

// A testbench
reg  in=0;
wire out1;
wire r1;
wire out2;
wire r2;
initial begin
	#10 in <= 1;
	#10 in <= 0;
	#20 in <= 1;
	#20 in <= 0;
	$display ("Hello world! The current time is (%0d ps)", $time);
	#50 $finish;            // Quit the simulation
end

func inst1 ( 
    .clk(clk),
    .rstn(rstn),
    .in(in),
    .r1(r1),
    .out1(out1),
    .r2(r2),
    .out2(out2));   // Sub-modules work too.

endmodule

module func(input clk,input rstn,input in,output reg r1,output reg r2,output reg out1,output reg out2);

always@(posedge clk)
begin
    if (in == 1'b1)begin 
        r1 = 1'b1; 
    end 
    else begin
        r1 = 1'b0;
    end
    if (r1 == 1'b1) begin
        out1 = 1'b1;   
    end 
    else begin
        out1=1'b0;  
    end
end

always@(posedge clk) begin 
    if (in == 1'b1)
        r2 <= 1'b1;
    else
        r2 <= 1'b0;
    
    if (r2 == 1'b1)  
        out2<= 1'b1;
    else 
        out2<= 1'b0;  
    end


`probe(in);	// Sub-modules can also have `probe()
`probe(r1);
`probe(out1);
`probe(r2);
`probe(out2);

endmodule
上述代码的仿真波形如下图所示：

非阻塞(Non_Blocking)赋值（<=），块结束后才完成赋值操作，值并不是立刻就改变的。

阻塞(Blocking)赋值方式( = )，值在赋值语句执行完后立刻就改变的。