四位串行加法器:
被加数a,加数b,低位进位ci,和数s,进位co.
Verilog代码:
module cxjfq(a,b,ci,s,co);
input[3:0] a,b;
input ci;
output[3:0] s;
output co;
assign {co,s} = a+b+ci;
endmodule
仿真结果:
四位串行加法器:
被加数a,加数b,低位进位ci,和数s,进位co.
Verilog代码:
module cxjfq(a,b,ci,s,co);
input[3:0] a,b;
input ci;
output[3:0] s;
output co;
assign {co,s} = a+b+ci;
endmodule
仿真结果:
转载于:https://www.cnblogs.com/Sagoo/p/3219234.html