83优先编码器真值表:
Verilog代码:
module yxbm83(en,d,q);
input en;
input[7:0] d;
output[2:0] q;
reg[2:0] q;
always@(en,d)
begin
if(en==1'b1)
begin
q <= 3'b111;
end
else
begin
if(d[7]==1'b0)
begin
q <= 3'b000;
end
else if(d[6]==1'b0)
begin
q <= 3'b001;
end
else if(d[5]==1'b0)
begin
q <= 3'b010;
end
else if(d[4]==1'b0)
begin
q <= 3'b011;
end
else if(d[3]==1'b0)
begin
q <= 3'b100;
end
else if(d[2]==1'b0)
begin
q <= 3'b101;
end
else if(d[1]==1'b0)
begin
q <= 3'b110;
end
else if(d[0]==1'b0)
begin
q <= 3'b111;
end
end
end
endmodule
仿真结果: