VCLP的使用

I. VCLP 的阶段

II. UPF Design FLow

VCLP  At RTL-level，VC LP UPF checks help in identifying power  intent issues early in the design life-cycle and enable you to arrive at a clean UPF before starting the design flow.  VCLP UPF checks ensure that the UPF is complete and the design conforms to all the isolation and level shifter rules for all power-modes.

At Netlist level, the VC LP UPF and functional(architectural) checks ensure that the netlist is consistent with UPF in structure and function.

The VC LP Power Ground checks help validate the power network implementation by verifying if the power/ground pin connectivity in the post-layout design is consistent with UPF and cell library.

Vclp RTL阶段需要读入待验证的模块的filelist，RTL文件的读入方式是通过read_file –vcs、 analyze –vcs、elaborate –vcs 这些阶段，待读入的文件通过rtl_filelist进行设置。

设置的脚本set_lib.tcl set rtl_filelist 设置待读入的文件，通过common_setup.tcl设置DESIGN_NAME

读入UPF文件read_upf Makefile 设置通过UPF_RTL ?= */win2030_dsp_subsys.upf

check_lp阶段使用check_lp –stage upf、 check_lp –stage design

report_lp阶段报告UPF目前存在的问题，这些问题可以通过查找 VC_Low_power_Message_Reference查找问题

 Start with logic and specification

 Define Domains

 Define Power States

 Embellish designs with:

-Domain definitions

  .Select elements

  .Provide Control and Power

-Domain boundary elements

  .Level shifters

  .Isolation

-Identify Controlled Elements

  .Retention

  .Switches

-Provide interconnect

-Logical Verification

-Implementation

-Validation

set_scope top

create_power_domain top_power_domain –include_scope

create_supply_net VDD_SOC –domain top_power_domain

connect_supply_net VDD_SOC –ports {pad_VDD_SOC}

create_supply_net VSS_SOC –domain top_power_domain

connect_supply_net VSS_SOC –ports {pad_VSS_SOC}

create_power_domain my_power_domain –elements {U1}

create_supply_net sw_vdd –domain my_power_domain

set_domain_supply_net my_power_domain

 –primary_power_net sw_vdd

 –primary_ground_net VSS_SOC

create_power_switch my_power_switch –domain my_power_domain

 -input_supply_port {my_sw_input_port  VDD_SOC}

-output_supply_port {my_sw_output_port  sw_vdd}

-control_port {my_sw_control_port  pwr_req}

-ack_port {my_ack_port pwr_ack}

-on_state {pwr_on_state my_input_port {my_sw_control_port == 1 })}

-off_state {pwr_off_state {my_sw_control_port == 0}}

set_retention my_retention_strategy –domain my_power_domain –retention_power_net VDD_SOC set_retention_controlmy_retention_strategy –domain my_power_domain –save_signal {retain_n negedge}

–restore_signal {retain_n posedge}

set_isolation my_power_domain_isolation –domain my_power_domain –isolation_power_net VDD_SOC -clamp_value 0

set_isolation_control my_power_domain_isolation –domain my_power_domain -isolation_signal isolate -location self

set_level_shifter my_level_shifter_strategy –domain Domain_A –applies_to outputs –location fanout

set_scope top

create_power_domain top_power_domain –include_scope

create_supply_net VDD_SOC –domain top_power_domain

connect_supply_net VDD_SOC –ports {pad_VDD_SOC}

create_supply_net VSS_SOC –domain top_power_domain

connect_supply_net VSS_SOC –ports {pad_VSS_SOC}

create_power_domain my_power_domain –elements {U1}

create_supply_net sw_vdd –domain my_power_domain

set_domain_supply_net my_power_domain

 –primary_power_net sw_vdd

 –primary_ground_net VSS_SOC

create_power_switch my_power_switch –domain my_power_domain

 -input_supply_port {my_sw_input_port  VDD_SOC}

-output_supply_port {my_sw_output_port  sw_vdd}

-control_port {my_sw_control_port  pwr_req}

-ack_port {my_ack_port pwr_ack}

-on_state {pwr_on_state my_input_port {my_sw_control_port == 1 })}

-off_state {pwr_off_state {my_sw_control_port == 0}}

set_retention my_retention_strategy –domain my_power_domain –retention_power_net VDD_SOC set_retention_controlmy_retention_strategy –domain my_power_domain –save_signal {retain_n negedge}

–restore_signal {retain_n posedge}

set_isolation my_power_domain_isolation –domain my_power_domain –isolation_power_net VDD_SOC -clamp_value 0

set_isolation_control my_power_domain_isolation –domain my_power_domain -isolation_signal isolate -location self

set_level_shifter my_level_shifter_strategy –domain Domain_A –applies_to outputs –location fanout

UPF creates

        Power nets

        Power ports

        Power swithes

        Isolation cells

        Level shifters

UPF Connects Power Nets to

        Power ports

        Power switches

        Isolation cells

        Level shifters

        Retention Flops

        Standard cell logic

UPF converts flops to retention flops

UPF connects control signals to

         Power switches

         Isolation cells

         Retention flops

ON:

        Both primary power and ground are ON

         Supply port drives a voltage value

OFF:

        Primary power and/or ground are OFF

        Voltage value is irrelevant

PARTIAL_ON

        For power-aware  models may more accurately reflect switching capacitive transition

         Useful in supply net resolution (coming up)

Event:

         Power net to logic block switched off

         And/Or Ground net switched off

Logic behavior is disabled from evaluation

          On inputs may transition,but events do not trigger powered down logic to evaluate

 Wires driven by powered down logic are corrupted

          X for logic types

          Default initial value all other types

           Pass through wires are not effected

Registers in the powered down logic are corrupted        

       

Event:

        Power and Ground are switched ON

Logic behavior is enabled for evaluation:

        Combinatorial logic and latches are re-evaluated

        Continuous assignments are re-evaluated

        Flops (edge-triggerd logic) evaluated on next active edge

Wire values are updated as assignments are evaluated

Register values remain unchanged until controlling logic is re-evaluated

Power down/up semantics applies for:

          Logic connected to primary power&ground

          Retention registers connected to retention power & ground

                If a retention supply is swiched off during retention,the retained value is corrupted and save/restore is disabled

           Isolation logic connected to isolation power & ground

                 If an isolation supply is switched off,then the isolated output is corrupted

Other supplies may be defined in UPF

          But,UPF defines no power down/up semantics for these supplies

          The logic connected to these supplies must be power-aware

                  .Explicitly handle corruption and evaluation (switching enabling/disabling)

each IP comes with a UPF:

        formal description of power within IP

        to be used ‘as is’ or merged on the top level

Incremental change from version to version of an IP block

        reuse of existing UPF

Power configuration of ‘family members’ on top level

       upper level UPF links UPF of IPs together and defines PST

        Power and Ground are switched ON

See UPF commands:

      merge_power_domains

       option ‘-scope’ defines hierarchical scope of UPF commands

给出UPF文件之前需要画出power arch结构图，power arch结构图需要标明power domain、power supply、需要画出power_switch需要给出power_switch的供电，同时需要添加isolation cell，通常设置output接口的clamp值

如下图

需要定义supply_net supply_port 需要定义POWER GROUD,supply_net 是内部定义的net线，supply_port是外部port点

create internal power pin 使用create_supply_net VDDCORE_cluster_i –resolve parallel

定义内部的power pin，associate_supply_set –handle (将电源集、电源开关或策略电源集句柄相关联)，

set_isolation             需要定义在哪个domain，isolation_supply_set isolation的供电

isolation_signal         isolation的控制信号

isolation_sense          isolation的

clamp_value               clamp到什么上去

location 有多种选择可以放在self也可以放在pa

applies_to   输入还是输出

后端使用的UPF的upf version 2.1

验证仿真在sim选项上使用-upf *.upf 加上去，supply(VDD_SOC,1,)这样