soc的核间通信机制：Mailbox 原理和寄存器说明

Interprocessor Communication

The MPU and DSP processors communicate with each other via a
mailbox-interrupt mechanism. This mechanism provides a very flexible
software protocol between the processors.
mailbox其实是多核处理器soc上，核与核之间互相发中断的机制，由于核与核之间可能存在不同的业务，故硬件上设计分配一两个中断已经无法满足业务的需求，软件拓展起来很困难，所以mailbox可以理解为软件可自由定义的中断模块。

Mailbox Register Data Structure

本文内容摘抄自omap1510公开的用户手册，其他厂家soc的mailbox设计可能有所差异，但是用法大同小异。
在omap1510这个soc中，有两个处理器，下文均以ARM（或MPU） 和DSP来代替
1：MPU ARM925T
2：DSP TMS320C55x

There are four sets of mailbox registers: two for the MPU to send messages and issue an interrupt to the DSP, the other two for the DSP to send messages and issue an interrupt to the MPU. Each set of mailbox registers consists of two 16-bit registers and a 1-bit flag register. The interrupting processor can use one 16-bit register to pass a data word to the interrupted processor and the other 16-bit register to pass a command word.
在向命令字处理器写入时，会对另外一个处理器产生一个中断，中断标志寄存器对应flag会被置起。共享数据是可选的，由软件决定，但数据的写入必须写在写mailbox寄存器之前。

soc为每个核分配了两个mailbox中断：ARM2DSP1/ARMDSP2，DSP2ARM1/DSP2ARM2， 一个mailbox中断可以有16bit自定义，总共有32个。ARM2DSP1和ARMDSP2中断在DSP中分别注册为INT5和INT19。DSP2ARM1和DSP2ARM2中断分别映射到MPU level 1中断处理程序IRQ10和IRQ11。

被中断的处理器必须通过读取中断寄存器来确认中断。读取后，中断被复位，中断对应的1bit flag被清。

mailbox产生的中断触发类型是边缘触发，当在中断处理函数中mask了对应的interrupt， 再去写command register也无法产生中断，但是command flag会被置位，这个中断的处理流程跟普通的中断流程也基本一致。
The following software setup procedures are provided as an example.

1. System software initializes all four of the mailboxes (during powerup or when the system must put the mailboxes in a known state).
2. System software enables the interrupt mask in the respective interrupt handler associated with each processor.
3. The interrupting processor writes to the mailbox data location with the data word information when it must alert to the word for the other processor (at this point, the associated word command for the other processor should not have been set yet).
4. The interrupting processor writes to the mailbox command word a predefined command (predefined and understood by both processors). This write issues the interrupt to the other processor.
5. In response to the interrupt, the interrupted processor acknowledges the interrupt by reading the mailbox registers. Reading the two locations is performed by the software protocol; the system software must read the data first and then read the command register (the associated interrupt and 1-bit flag register are cleared upon read).
6. System software examines the data and command words to determine what to do.
7. System software calls an interrupt service routine (ISR), to do whatever processing is necessary. System software returns to normal processing.

寄存器描述