CORDIC arithmetic

传统CORDIC算法code

Verilog代码：
时钟为50Mhz；
输出设置均设置为有符号数，主要是因为计算CORDIC算法时，需要判断Z通道的符号，来得到迭代过程中旋转方向。

然后根据缩放因子和arctan 2^-n 的预定义并乘以2^16 来进行后续计算，根据迭代方程写出代码；最后将（0度到90度）中正弦值与余弦值来扩大至（0度至360度)的正弦值与余弦值。

module cordic(
	input clk_50M,
	input rst,
	input [31:0] angle,
	output reg signed [31:0] sin,
	output reg signed [31:0] cos,
	output reg signed [31:0] error);
`define rot0 32'd2949_120
`define rot1 32'd1740_967
`define rot2 32'd9198_79
`define rot3 32'd4669_45
`define rot4 32'd2343_78
`define rot5 32'd1173_04
`define rot6 32'd5866_6
`define rot7 32'd2933_4
`define rot8 32'd1466_8
`define rot9 32'd7334
`define rot10 32'd3667
`define rot11 32'd1833
`define rot12 32'd917
`define rot13 32'd458
`define rot14 32'd229
`define rot15 32'd115

parameter pipeline =16;
parameter k=32'd39797;

reg signed [31:0] x0,y0,z0;
reg signed [31:0] x1,y1,z1;
reg signed [31:0] x2,y2,z2;
reg signed [31:0] x3,y3,z3;
reg signed [31:0] x4,y4,z4;
reg signed [31:0] x5,y5,z5;
reg signed [31:0] x6,y6,z6;
reg signed [31:0] x7,y7,z7;
reg signed [31:0] x8,y8,z8;
reg signed [31:0] x9,y9,z9;
reg signed [31:0] x10,y10,z10;
reg signed [31:0] x11,y11,z11;
reg signed [31:0] x12,y12,z12;
reg signed [31:0] x13,y13,z13;
reg signed [31:0] x14,y14,z14;
reg signed [31:0] x15,y15,z15;
reg signed [31:0] x16,y16,z16;

always@(posedge clk_50M or negedge rst)
begin
	if(!rst)
	begin
		x0<=0;
		y0<=0;
		z0<=0;
	end
	else
	begin
		x0<=k;
		y0<=0;
		z0<=angle[15:0]<<16