vivado FSM_SAFE_STATE

FSM_SAFE_STATE
此属性可以在RTL和XDC中设置。
Vivado合成工具支持在各种情况下提取有限状态机（FSM）
配置由FSM_ENCODING属性或-FSM_traction确定
Vivado合成的命令行选项。请参阅《Vivado设计套件用户指南》：
综合（UG901）[参考文献18]以获取更多信息。
状态机可以进入无效或“不可访问”状态，导致设计
失败FSM_SAFE_STATE告诉合成将逻辑插入状态机，状态机检测是否
存在无效状态，然后在下一个时钟周期将其置于已知状态。如果FSM
如果进入无效状态，FSM_SAFE_state属性将定义一个恢复状态，以便在以下情况下使用
在Vivado合成工具中合成FSM。
提示：在提供FSM状态的安全恢复的同时，此特性会影响合成的质量
结果，通常会导致更大面积的性能降低。

Values

• reset_state : Return the state machine to the RESET state, as determined by the

Vivado synthesis tool.

• power_on_state : Return the state machine to the POWER_ON state, as determined

by the Vivado synthesis tool.

• default_state : Return the state machine to the default state, as defined by the state

machine; even if that state is unreachable, using Hamming-2 encoding detection for

one bit/flip.

• auto_safe_state : implies Hamming-3 encoding.

Syntax

Verilog Example

(* fsm_safe_state = "reset_state" *) reg [2:0] state;

(* fsm_safe_state = "reset_state" *) reg [7:0] my_state;

VHDL Example

type count_state is (zero, one, two, three, four, five, six, seven);

signal my_state : count_state;

attribute fsm_safe_state : string;

attribute fsm_safe_state of my_state : signal is "power_on_state";

XDC Example

set_property fsm_safe_state reset_state [get_cells state_reg*]