vivado GATED_CLOCK

门控时钟
使用GATED_CLOCK属性启用Vivado合成以执行门控转换
时钟。转换时钟门控逻辑，以便在可用时利用触发器启用引脚。这
优化可以消除时钟树上的逻辑，简化网表。
此RTL属性指示工具门控逻辑中的哪个信号是时钟。
该属性放置在作为时钟的信号或端口上。
此属性只能在RTL中设置。
注意：您还可以在Vivado合成工具中使用一个开关，指示该工具尝试
转变
synth_design-gated_clock_conversion打开
架构支持
所有架构。
适用对象
•时钟输入端口
•时钟信号

Values

• FALSE : Disables the gated clock conversion.

• TRUE : Gated clock conversion occurs if the GATED_CLOCK attribute is set in the RTL

code. This option gives you more control of the outcome.

• AUTO : Gated clock conversion occurs if either of the following events are true:

°

The GATED_CLOCK property is set to TRUE

°

The Vivado synthesis can detect the gate and there is a valid clock constraint set.

This option lets the tool make decisions.

Syntax

Verilog Example

(* gated_clock = "true" *) input clk;

VHDL Example

entity test is port (

in1, in2 : in std_logic_vector(9 downto 0);

en : in std_logic;

clk : in std_logic;

out1 : out std_logic_vector( 9 downto 0));

attribute gated_clock : string;

attribute gated_clock of clk : signal is "true";

end test;