RLOC_ORIGIN属性为相对放置的对象提供绝对位置或LOC
RTL设计中的宏(RPM)。有关定义RPM和使用
RLOC_ORIGIN属性,请参阅《Vivado Design Suite用户指南:使用约束》
(UG903)[参考文献19]。
RPM是通过使用H_set、HU_set或U_set将设计元素分配给集合来定义的
RTL设计中的优点。然后,为设计元素分配一个相对位置
彼此使用RLOC属性。您可以定义任何元素的相对位置
相对于集合中的其他元素,在集合内,无论最终的位置如何
将整个组转移到目标设备上。
定义了RPM的元素及其相对位置后,RLOC_ORIGIN
属性允许您定义RPM在目标设备上的绝对位置。这个
RLOC_ORIGIN属性在合成过程中转换为LOC约束。
在Vivado设计套件中,RLOC_ORIGIN属性定义了
RPM。这通常是RLOC属性为X0Y0的设计元素。每剩余
RPM集中的单元使用其相对位置(RLOC)作为
从组原点(RLOC_origin)偏移。
架构支持
所有架构。
适用对象
•RTL源文件中的实例。
价值观
使用基于SLICE的XY坐标系指定相对位置约束。
RLOC_ORIGIN=XmYn
哪里:
•m是一个整数,表示目标设备上的绝对X坐标
RPM的左下角。
•n是一个整数,表示目标设备上的绝对Y坐标
RPM的左下角。
Syntax
Verilog Syntax
The RLOC_ORIGIN property is a Verilog attribute defining the absolute placement of an
RPM on the target device. Place the Verilog attribute immediately before the instantiation
of a logic element.
(* RLOC_ORIGIN = "XmYn", HU_SET = "h0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));
Verilog Example
The following top-level Verilog module defines the RLOC_ORIGIN property for the ffs
modules in the design.
module top
(
input clk,
input d,
output q
);
wire c1, c2;
(* RLOC_ORIGIN = "X1Y1", KEEP_HIERARCHY = "YES" *) ffs u0 (clk, d, c1);
(* RLOC_ORIGIN = "X3Y3", KEEP_HIERARCHY = "YES" *) ffs u1 (clk, c1, c2);
(* RLOC_ORIGIN = "X5Y5", KEEP_HIERARCHY = "YES" *) ffs u2 (clk, c2, q);
endmodule // top
The following example is very similar to the first, except that the RLOC_ORIGIN is only
assigned to the first ffs module, u0, and the rest are defined with RLOC properties for
relative placement:
module top
(
input clk,
input d,
output q
);
wire c1, c2;
// what would happen if the origin places the RPM outside
// device?
(* RLOC_ORIGIN = "X74Y15", RLOC = "X0Y0" *) ffs u0 (clk, d, c1);
(* RLOC = "X1Y1" *) ffs u1 (clk, c1, c2);
(* RLOC = "X2Y2" *) ffs u2 (clk, c2, q);
endmodule // top
VHDL Syntax
Declare the VHDL constraint as follows:
attribute RLOC_ORIGIN: string;
Specify the VHDL constraint as follows:
attribute RLOC_ORIGIN of {component_name | entity_name | label_name} :
{component|entity|label} is “XmYn”;
Where:
• {
component_name
|
entity_name
|
label_name
} is a choice of one design element.
• {
component
|
entity
|
label
} is the instance ID of the design element.
•
XmYn
defines the RLOC_ORIGIN value for the specified design element.
XDC Syntax
The RLOC_ORIGIN property translates to the LOC property in the synthesized design. You
can specify the LOC property of RPMs by placing one of the elements of the RPM onto the
target device. The other elements of the RPM will be placed relative to that location, and
assigned to LOC property.