异步FIFO采用Gray Counter产生读写地址,Empty/Full信号的产生也与Gray Counter的最高两位相关。
`timescale 1ns / 1ps // // Company: SEU.IC // Engineer: Ray // // Create Date: 21:58:22 03/28/2011 // Design Name: Gray Counter // Module Name: GrayCounter // Revision 0.01 - File Created // module GrayCounter( Clock, Reset_in, Enable_in, GrayCount_out ); parameter COUNTER_WIDTH = 5; input Clock; input Reset_in; input Enable_in; output [COUNTER_WIDTH - 1 : 0]GrayCount_out; reg [COUNTER_WIDTH - 1 : 0] BinaryCount; wire [COUNTER_WIDTH - 1 : 0]GrayCount_out; always @(posedge Clock or negedge Reset_in) begin if(!Reset_in) BinaryCount <&# |