系列文章目录
前言
命令行传参启动不同的Sequence,进而构建不同的Test,实现Sequence与Test的对应。
一、采用uvm_cmdline_processor传参启动不同的Sequence
1.相关的代码实现实例:
class learn_agent extends uvm_agent;
string learn_config;
learn_sequencer learn_sqr;
learn_driver learn_dri;
learn_monitor learn_mon;
uvm_cmdline_processor ucp=cmdline_processor::get_inst();
uvm_analysis_port #(learn_transaction) learn_ap;
function new(string name,uvm_componet parent);
super.new(name,parent);
`uvm_info("learn_agent","learn_agent is ready",UVM_LOW)
endfunction
`uvm_component_utils(learn_agent)
extern virtual function void build_phase(uvm_phase phase);
extern virtual fucntion void connet_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);
endclass
function void learn_agent::build_phase(uvm_phase phase);
super.build_phase(phase);
if(is_active==UVM_ACTIVE)begin //在env中,可以控制:i_agt.is_active = UVM_ACTIVE
learn_sqr=learn_sequencer::type_id::create("learn_sqr",this);
//注意这个create(“learn_sqr”)才是最后UVM_TREE中的实例名,如果改成create(“learn_sequencer”)也不会报错,只是UVM_TREE中的名称会变成learn_sequencer
learn_dri=learn_driver::type_id::create("learn_dri",this);
end
learn_mon=learn_monitor::type_id::create("learn_mon",this);
learn_ap=new("learn_ap",this);
endfunction
function void learn_agent::connect_phase(uvm_phase phase);
super.connect_phase(phase);
if(is_active==UVM_ACTIVE)begin
learn_dri.seq_item_port.connect(learn_dri.seq_item_export);
learn_ap=learn_mon.mon_ap_in;
//monitor中例化两个port