module top(clk, button, switch, led, segment, digit_anode);
input wire clk;
input wire [11:0] button;
input wire [15:0] switch;
output wire [15:0] led;
output wire [15:0] segment;
output wire [11:0] digit_anode;
reg [15:0] disp_num;
reg [31:0] disp_num32b;
wire [3:0] blink, dots;
wire [11:0] button_out;
wire clk_500ms;
timer_500ms I1(clk, clk_500ms);
display I2(clk, disp_num, dots, blink, clk_500ms, digit_anode[3:0], segment[7:0]);
display32bits I3(clk,disp_num32b,digit_anode[11:4],segment[15:8]);
anti_jitter a0(clk,button[0],button_out[0]);
anti_jitter a1(clk,button[1],button_out[1]);
anti_jitter a2(clk,button[2],button_out[2]);
anti_jitter a3(clk,button[3],button_out[3]);
anti_jitter a4(clk,button[4],button_out[4]);
anti_jitter a5(clk,button[5],button_out[5]);
anti_jitter a6(clk,button[6],button_out[6]);
anti_jitter a7(clk,button[7],button_out[7]);
anti_jitter a8(clk,button[8],button_out[8]);
anti_jitter a9(clk,button[9],button_out[9]);
anti_jitter a10(clk,button[10],button_out[10]);
anti_jitter a11(clk,button[11],button_out[11]);
initial disp_num <= 32'b0001_0010_0011_0100; // 0x123423456789
assign led = switch;
assign {dots, blink} = {~switch[7:4], switch[3:0]};
always @(posedge button_out[0]) disp_num[ 3: 0] <= disp_num[ 3: 0] + 1;
always @(posedge button_out[1]) disp_num[ 7: 4] <= disp_num[ 7: 4] + 1;
always @(posedge button_out[2]) disp_num[11: 8] <= disp_num[11: 8] + 1;
always @(posedge button_out[3]) disp_num[15:12] <= disp_num[15:12] + 1;
always @(posedge button_out[4]) disp_num32b[3:0] <= disp_num32b[3:0] + 1;
always @(posedge button_out[5]) disp_num32b[7:4] <= disp_num32b[7:4] + 1;
always @(posedge button_out[6]) disp_num32b[11:8] <= disp_num32b[11:8] + 1;
always @(posedge button_out[7]) disp_num32b[15:12] <= disp_num32b[15:12] + 1;
always @(posedge button_out[8]) disp_num32b[19:16] <= disp_num32b[19:16] + 1;
always @(posedge button_out[9]) disp_num32b[23:20] <= disp_num32b[23:20] + 1;
always @(posedge button_out[10]) disp_num32b[27:24] <= disp_num32b[27:24] + 1;
always @(posedge button_out[11]) disp_num32b[31:28] <= disp_num32b[31:28]+1;
endmodule
module timer_500ms
(input clk,
output reg clk_500ms);
reg [24:0] cnt;
initial begin
cnt [24:0] <=0;
clk_500ms <= 0;
end
always@(posedge clk)
if(cnt>=12_500_500) begin
cnt<=0;
clk_500ms <= ~clk_500ms;
end
else begin
cnt<=cnt+1;
end
endmodule
module display(
input wire clk,
input wire [15:0] digit,//显示的数据
input wire [3:0] dots,
input wire [3:0] blink,
input wire clk_500ms,
output reg [ 3:0] node, //4个数码管的位选
output reg [ 7:0] segment);//七段+小数点
reg [4:0] code = 5'b0;
reg [15:0] count = 15'b0;
initial node = 4'b1111;
always @(posedge clk) begin
case ({clk_500ms,count[15:14]})
//与(count[1:0])的不同起到分频的作用
3'b000 : begin
node <= 4'b1110|blink;
code <= {~dots[0],digit[3:0]};
end
3'b001 : begin
node <= 4'b1101|blink;
code <= {~dots[1],digit[7:4]};
end
3'b010 : begin
node <= 4'b1011|blink;
code <= {~dots[2],digit[11:8]};
end
3'b011 : begin
node <= 4'b0111|blink;
code <= {~dots[3],digit[15:12]};
end
3'b100 : begin
node <= 4'b1110;
code <= {~dots[0],digit[3:0]};
end
3'b101 : begin
node <= 4'b1101;
code <= {~dots[1],digit[7:4]};
end
3'b110 : begin
node <= 4'b1011;
code <= {~dots[2],digit[11:8]};
end
3'b111 : begin
node <= 4'b0111;
code <= {~dots[3],digit[15:12]};
end
endcase
case (code)
5'b00000: segment <= 8'b11000000;
5'b00001: segment <= 8'b11111001;
5'b00010: segment <= 8'b10100100;
5'b00011: segment <= 8'b10110000;
5'b00100: segment <= 8'b10011001;
5'b00101: segment <= 8'b10010010;
5'b00110: segment <= 8'b10000010;
5'b00111: segment <= 8'b11111000;
5'b01000: segment <= 8'b10000000;
5'b01001: segment <= 8'b10010000;
5'b01010: segment <= 8'b10001000;
5'b01011: segment <= 8'b10000011;
5'b01100: segment <= 8'b11000110;
5'b01101: segment <= 8'b10100001;
5'b01110: segment <= 8'b10000110;
5'b01111: segment <= 8'b10001110;
5'b10000: segment <= 8'b01000000;
5'b10001: segment <= 8'b01111001;
5'b10010: segment <= 8'b00100100;
5'b10011: segment <= 8'b00110000;
5'b10100: segment <= 8'b00011001;
5'b10101: segment <= 8'b00010010;
5'b10110: segment <= 8'b00000010;
5'b10111: segment <= 8'b01111000;
5'b11000: segment <= 8'b00000000;
5'b11001: segment <= 8'b00010000;
5'b11010: segment <= 8'b00001000;
5'b11011: segment <= 8'b00000011;
5'b11100: segment <= 8'b01000110;
5'b11101: segment <= 8'b00100001;
5'b11110: segment <= 8'b00000110;
5'b11111: segment <= 8'b00001110;
default: segment <= 8'b00000000;
endcase
count <= count + 1;
end
endmodule
module display32bits(clk,disp_num,digit_anode,segment);
input clk;
input [31:0] disp_num;
output [7:0] digit_anode;
output [7:0] segment;
reg [7:0] digit_anode;
reg [7:0] segment;
reg [12:0] cnt=0;
wire [31:0] disp_num;
reg [3:0] num;
always@(posedge clk)begin
case(cnt[12:10])
3'b000:begin
digit_anode <= 8'b11111110;
num <= disp_num[3:0];
end
3'b001:begin
digit_anode <= 8'b11111101;
num <= disp_num[7:4];
end
3'b010:begin
digit_anode <= 8'b11111011;
num <= disp_num[11:8];
end
3'b011:begin
digit_anode <= 8'b11110111;
num <= disp_num[15:12];
end
3'b100:begin
digit_anode <= 8'b11101111;
num <= disp_num[19:16];
end
3'b101:begin
digit_anode <= 8'b11011111;
num <= disp_num[23:20];
end
3'b110:begin
digit_anode <= 8'b10111111;
num <= disp_num[27:24];
end
3'b111:begin
digit_anode <= 8'b01111111;
num <= disp_num[31:28];
end
endcase
case(num)
4'b0000:segment<=8'b11000000;
4'b0001:segment<=8'b11111001;
4'b0010:segment<=8'b10100100;
4'b0011:segment<=8'b10110000;
4'b0100:segment<=8'b10011001;
4'b0101:segment<=8'b10010010;
4'b0110:segment<=8'b10000010;
4'b0111:segment<=8'b11111000;
4'b1000:segment<=8'b10000000;
4'b1001:segment<=8'b10010000;
4'b1010:segment<=8'b10111111;
4'b1011:segment<=8'b01111111;
default:segment<=8'b11111111;
endcase
end
always@(posedge clk) begin
cnt<=cnt+1;
end
endmodule
module anti_jitter
(input wire clk,
input wire button,
output reg pbreg);
reg [7:0] pbshift;
wire clk_1ms;
timer_1ms m0(clk, clk_1ms);
always@(posedge clk_1ms) begin
pbshift=pbshift<<1;//左移1位
pbshift[0]=button;
if (pbshift==0)
pbreg=0;
if (pbshift==8'hFF)// pbshift八位全为1
pbreg=1;
end
endmodule
module timer_1ms
(input wire clk,
output reg clk_1ms);
reg [15:0] cnt;
initial begin
cnt [15:0] <=0;
clk_1ms <= 0;
end
always@(posedge clk)
if(cnt>=25000) begin
cnt<=0;
clk_1ms <= ~clk_1ms;
end
else begin
cnt<=cnt+1;
end
endmodule
NET "clk" LOC = "t9" ;
NET "digit_anode[0]" LOC = "D14" ;
NET "digit_anode[1]" LOC = "G14" ;
NET "digit_anode[2]" LOC = "F14" ;
NET "digit_anode[3]" LOC = "E13" ;
NET "digit_anode[4]" LOC = "B11" ;
NET "digit_anode[5]" LOC = "A10" ;
NET "digit_anode[6]" LOC = "B10" ;
NET "digit_anode[7]" LOC = "A9" ;
NET "digit_anode[8]" LOC = "A8" ;
NET "digit_anode[9]" LOC = "B8" ;
NET "digit_anode[10]" LOC = "A7" ;
NET "digit_anode[11]" LOC = "B7" ;
NET "button[0]" LOC = "M13" ;
NET "button[1]" LOC = "M14" ;
NET "button[2]" LOC = "L13" ;
NET "button[3]" LOC = "L14" ;
NET "button[4]" LOC = "E6" ;
NET "button[5]" LOC = "D5" ;
NET "button[6]" LOC = "C5" ;
NET "button[7]" LOC = "D6" ;
NET "button[8]" LOC = "C6" ;
NET "button[9]" LOC = "E7" ;
NET "button[10]" LOC = "C7" ;
NET "button[11]" LOC = "D7" ;
NET "switch[0]" LOC = "F12" ;
NET "switch[1]" LOC = "G12" ;
net "switch[2]" LOC = "H14";
net "switch[3]" loc="H13";
net "switch[4]" loc="J14";
net "switch[5]" loc="J13";
net "switch[6]" loc="K14";
NET "switch[7]" LOC = "K13";
NET "switch[8]" LOC = "H4" ;
NET "switch[9]" LOC = "E4" ;
net "switch[10]" LOC = "G5";
net "switch[11]" loc="F4";
net "switch[12]" loc="E3";
net "switch[13]" loc="G4";
net "switch[14]" loc="F3";
NET "switch[15]" LOC = "M10";
NET "led[0]" loc = "k12";
net "led[1]" loc = "p14";
net "led[2]" loc = "l12";
net "led[3]" loc = "n14";
net "led[4]" loc = "p13";
net "led[5]" loc = "n12";
net "led[6]" loc = "p12";
net "led[7]" loc = "p11";
NET "led[8]" LOC = "b1" ;
NET "led[9]" LOC = "c1" ;
NET "led[10]" LOC = "c2" ;
NET "led[11]" LOC = "r5" ;
NET "led[12]" LOC = "t5" ;
NET "led[13]" LOC = "r6" ;
NET "led[14]" LOC = "t8" ;
NET "led[15]" LOC = "n7" ;
NET "segment[0]" LOC = "E14" ;
NET "segment[1]" LOC = "G13" ;
NET "segment[2]" LOC = "N15" ;
NET "segment[3]" LOC = "P15" ;
NET "segment[4]" LOC = "R16" ;
NET "segment[5]" LOC = "F13" ;
NET "segment[6]" LOC = "N16" ;
NET "segment[7]" LOC = "P16" ;
NET "segment[8]" LOC = "C8" ;
NET "segment[9]" LOC = "D8" ;
NET "segment[10]" LOC = "C9" ;
NET "segment[11]" LOC = "D10" ;
NET "segment[12]" LOC = "A3" ;
NET "segment[13]" LOC = "B4" ;
NET "segment[14]" LOC = "A4" ;
NET "segment[15]" LOC = "B5" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE