vhdl_VHDL的完整形式是什么？

vhdl

VHDL：VHSIC(超高速集成电路)硬件描述语言 (VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language)

VHDL is an abbreviation of VHSIC Hardware Description Language in which VHSIC stands for Very High-Speed Integrated Circuit. VHDL is a language of hardware description that is used to create a model of physical hardware used in logic circuits like digital systems to appraise their arrangement, timing, and activities. It is not supposed to be bewildered with a programming language as it is not a programming language. In VHDL, a user can also define its data type and also apart from that there are some predefined data types in VHDL.

VHDL是VHSIC硬件描述语言的缩写，VHSIC代表超高速集成电路 。 VHDL是一种硬件描述语言，用于创建逻辑电路(如数字系统)中使用的物理硬件模型，以评估其布置，时序和活动。 它不应该被编程语言所迷惑，因为它不是一种编程语言。 在VHDL中，用户还可以定义其数据类型，除此之外， VHDL中还有一些预定义的数据类型。

历史 (History)

• In 1981, it was initially created by the U.S. Department of Defense.

  1981年，它最初是由美国国防部创建的。

• In June 2006, the so-called Draft 3.0 of VHDL-2006 was officially permitted by the VHDL Technical Committee of Accellera. This projected standard makes available for the use of various extensions that make the writing and arranging VHDL code simpler, at the same time cause to continue complete compatibility with the older versions also.

  2006年6月，Accellera VHDL技术委员会正式批准了所谓的VHDL-2006 3.0草案。 这个预计的标准可用于各种扩展程序，这些扩展程序使VHDL代码的编写和安排更加简单，同时还使它们继续与旧版本完全兼容。

• In February 2008, VHDL 4.0 was officially permitted by Accellera which is also unofficially known as VHDL 2008.

  在2008年2月，Accellera正式允许使用VHDL 4.0，这也被非正式地称为VHDL 2008。

• In 2008, for addition to IEEE 1076-2008, Accellera launched VHDL 4.0 to the IEEE for balloting.

  2008年，除了IEEE 1076-2008之外，Accellera向IEEE推出了VHDL 4.0以进行投票。

• In January 2009, the VHDL standard IEEE 1076-2008 was published.

  2009年1月，发布了VHDL标准IEEE 1076-2008。

Image source: https://www.doulos.com/knowhow/vhdl_designers_guide/design_flow_using_vhdl/

图片来源：https://www.doulos.com/knowhow/vhdl_designers_guide/design_flow_using_vhdl/

为什么要使用VHDL？ (Why Use VHDL?)

• It will proficiently enhance the efficiency if used in an appropriate mode and organized approach.

  如果以适当的方式和有组织的方法使用，它将有效地提高效率。

• It provides an advantage to use again a code as stated by the use of the user.

  再次使用用户使用说明的代码提供了一个优势。

• As electronic tools are enhancing and developing quickly, a user can shift to further highly developed tools by using VHDL.

  随着电子工具的快速发展和增强，用户可以使用VHDL转换为进一步开发的工具。

优点 (Advantages)

• It has implementable features.

  它具有可实现的功能。

• In the context of the system, it has authenticated specifications or Subcontracts.

  在系统的上下文中，它具有经过身份验证的规范或分包合同。

• Its functionality is apart from execution.

  它的功能与执行无关。

• It imitates early and handles complications fast.

  它可以尽早模仿并快速处理并发症。

• It discovers design substitutes.

  它发现设计替代品。

• It manufactures improved designs.

  它制造改进的设计。

• It has automatic synthesis and test generation (ATPG for ASICs).

  它具有自动综合和测试生成功能(用于ASIC的ATPG)。

• It enhances efficiency and productivity by cutting down the time-to-market.

  它通过缩短产品上市时间来提高效率和生产率。

• Its technology and tools are independent as however FPGA specifications may be unexploited.

  它的技术和工具是独立的，但是可能无法利用FPGA规范。

• It has transferable design data to look after investment.

  它具有可转移的设计数据来照顾投资。

缺点 (Disadvantages)

• It is a huge and complicated language and this is the reason it is difficult to learn and its execution is not simple.

  这是一门庞大而复杂的语言，这就是很难学习且执行起来不简单的原因。

• In comparison to other tools, tools used in VHDL are expensive.

  与其他工具相比，VHDL中使用的工具价格昂贵。

• It does not make available for use all kinds of features of the technology.

  它不能使该技术的所有功能均可用。

翻译自: https://www.includehelp.com/dictionary/vhdl-full-form.aspx

vhdl