verilog刷题笔记001

对于HDLBits 12-hour clock一题，可以使用阻塞式赋值可以使硬件描述代码按照顺序执行，实现类似计数器异步级联（即一个计数器的输出作为另一个计数器的时钟）的效果

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    always@(posedge clk)begin
        if(reset==1)begin
            hh <= 8'h12;
            mm <= 8'd0;
            ss <= 8'd0;
        end
        else begin
            if(ena==0)begin
                hh <= hh;
                mm <= mm;
                ss <= ss; 
            end
            else begin
                //阻塞式赋值使得先进行加一操作之后再依次判断
                //从而实现进位，可以减少always模块的重复使用
                ss[3:0] = ss[3:0] + 1'b1;
                if (ss[3:0] == 4'd10)begin
                    ss[3:0] = 0;
                    ss[7:4] = ss[7:4] + 1'b1;
                end
                if (ss[7:4] == 4'd6)begin
                    ss[7:4] = 0;
                    mm[3:0] = mm[3:0] + 1'b1;
                end
                if (mm[3:0] == 4'd10)begin
                    mm[3:0] = 0;
                    mm[7:4] = mm[7:4] +1'b1;
                end
                if (mm[7:4] == 4'd6)begin
                    mm[7:4] = 0;
                    hh[3:0] = hh[3:0] + 1'b1;
                end
                if (hh[3:0] == 4'd10)begin
                    hh[3:0] = 0;
                    hh[7:4] = hh[7:4] +1'b1;
                    
                end                
                if (hh[7:4] == 4'd1&&hh[3:0] == 3)begin                    
                    hh[7:0] = 8'd1;  
                end
                if (hh == 8'h12 && mm == 8'h00 && ss == 8'h00)begin
                    pm = ~pm;
                end
            end
        end
    end
    

endmodule