名称:汽车速度表设计AX301开发板验证VHDL代码
软件:QuartusII
语言:VHDL
代码功能:
汽车速度表设计 设计一个汽车速度表。车轮每转一圈会产生一个脉冲,每个脉冲代表1米的距离,根据单位时间的脉冲数可推算出汽车的速度。 要求:
(1)模拟产生车轮运转产生的脉冲信号并对其计数,用按键选择脉冲信号的不同
(2)每隔10秒读取一次脉冲计数器,并据此计算车速
(3)用数码管显示车速,单位Km/h
(4)给出超速警告
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
本代码已在AX301开发板验证,开发板如下,其他开发板可以修改管脚适配:
1. 工程文件
2. 程序文件
3. 程序编译
4. RTL图
管脚
5. Testbench
6. 仿真图
按键模块
控制模块
速度模块
报警模块
显示模块
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; --汽车速度表 ENTITY Speedometer IS PORT ( clk_50M : IN STD_LOGIC;--输入时钟50MHz key_1 : IN STD_LOGIC;--按键输入控制脉冲 key_2 : IN STD_LOGIC;--按键输入控制脉冲 key_3 : IN STD_LOGIC;--按键输入控制脉冲 beep : OUT STD_LOGIC;--超速报警指示灯 bit_select : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);--数码管位选 seg_select : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--数码管段选 ); END Speedometer; ARCHITECTURE behave OF Speedometer IS COMPONENT speed IS PORT ( clk : IN STD_LOGIC; pulse : IN STD_LOGIC; clk_en : IN STD_LOGIC; latch : IN STD_LOGIC; rst : IN STD_LOGIC; speed_num : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT div_freq IS PORT ( clk_50M : IN STD_LOGIC; clk_1000 : OUT STD_LOGIC ); END COMPONENT; COMPONENT div IS PORT ( clk : IN STD_LOGIC; clk_en : OUT STD_LOGIC; latch : OUT STD_LOGIC; rst : OUT STD_LOGIC ); END COMPONENT; COMPONENT alarm IS PORT ( clk : IN STD_LOGIC; beep : OUT STD_LOGIC; speed_num : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT key_ctrl IS PORT ( clk : IN STD_LOGIC; key_1 : IN STD_LOGIC; key_2 : IN STD_LOGIC; key_3 : IN STD_LOGIC; pulse : OUT STD_LOGIC ); END COMPONENT; COMPONENT display IS PORT ( clk : IN STD_LOGIC; speed_num : IN STD_LOGIC_VECTOR(7 DOWNTO 0); bit_select : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); seg_select : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; SIGNAL clk_en : STD_LOGIC; SIGNAL latch : STD_LOGIC; SIGNAL rst : STD_LOGIC; SIGNAL speed_num : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL pulse : STD_LOGIC; SIGNAL clk : STD_LOGIC; BEGIN --分频模块 i_div_freq : div_freq PORT MAP ( clk_50M => clk_50M, clk_1000 => clk ); --clk<=clk_50M; --按键控制脉冲输出 i_key_ctrl : key_ctrl PORT MAP ( clk => clk, key_1 => key_1, key_2 => key_2, key_3 => key_3, pulse => pulse ); --控制模块,输出控制信号 i_div : div PORT MAP ( clk => clk, clk_en => clk_en, latch => latch, rst => rst ); --速度计算模块 i_speed : speed PORT MAP ( clk => clk, pulse => pulse, clk_en => clk_en, latch => latch, rst => rst, speed_num => speed_num ); --数码管显示模块 i_display : display PORT MAP ( clk => clk, speed_num => speed_num, bit_select => bit_select, seg_select => seg_select ); --超速报警 i_alarm : alarm PORT MAP ( clk => clk, beep => beep, speed_num => speed_num ); END behave;